Displaying 13 results from an estimated 13 matches for "ilformat".
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2012 Apr 19
2
[LLVMdev] Tablegen to match a literal in an instruction
I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns.
What I am trying to do is take a register/register pattern and change it to a register/immediate.
So for example, I have this pattern:
class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace = "AMDIL";
dag OutOperandList = outs;
dag InOperandList = ins;
ILOpCode operation = op;
let Pattern = pattern;
let AsmString = !strconcat(asmstr, "...
2012 Apr 19
3
[LLVMdev] Tablegen to match a literal in an instruction
...lmow at amd.com>> wrote:
I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns.
What I am trying to do is take a register/register pattern and change it to a register/immediate.
So for example, I have this pattern:
class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace = "AMDIL";
dag OutOperandList = outs;
dag InOperandList = ins;
ILOpCode operation = op;
let Pattern = pattern;
let AsmString = !strconcat(asmstr, "...
2011 Dec 16
2
[LLVMdev] Vector immediates in tablegen w/o build_vector?
I have two patterns in tablegen that do look like the exact same thing:
Pat 1)
def MOV_v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst),
(ins i16imm:$val),
asm, [(set GPRV4I16:$dst, (build_vector (i16 imm:$val)))]>;
Pat 2)
def v4i16imm : Operand<v4i16>;
def MOV_v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst),
(ins v4i16imm:$val),
asm, [(set GPRV4I16:$dst, (v4...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...rote:
> I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns.
>
> What I am trying to do is take a register/register pattern and change it to a register/immediate.
> So for example, I have this pattern:
> class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
> : Instruction {
> let Namespace = "AMDIL";
> dag OutOperandList = outs;
> dag InOperandList = ins;
> ILOpCode operation = op;
> let Pattern = pattern;
> let A...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...>
> I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns.
>
> What I am trying to do is take a register/register pattern and change it to a register/immediate.
> So for example, I have this pattern:
> class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
> : Instruction {
> let Namespace = "AMDIL";
> dag OutOperandList = outs;
> dag InOperandList = ins;
> ILOpCode operation = op;
> let Pattern = pattern;
> let A...
2008 Nov 18
1
[LLVMdev] 32 bit boolean results
You can tell LLVM that you have "sign extended" setCC results (all
ones).
Dan
On Nov 18, 2008, at 5:33 PM, Eli Friedman wrote:
> On Tue, Nov 18, 2008 at 1:56 PM, Villmow, Micah
> <Micah.Villmow at amd.com> wrote:
>> The IR produces correct results, but my backend does not and the
>> only thing
>> I can think of is that the IR is treating the
2011 Mar 31
3
[LLVMdev] Assert in VerifySDNode
...torExtract<IL_vextract>;
// Class that handles the various vector extract patterns
multiclass VectorExtract<SDNode OpNode> {
...
def _v4i32 : ExtractVectorClass<GPRI32, GPRV4I32, OpNode>;
...
}
class ExtractVectorClass<RegisterClass DReg, RegisterClass SReg, SDNode OpNode>
: ILFormat<IL_OP_MOV, (outs DReg:$dst), (ins SReg:$src0, i32imm:$src1),
"mov $dst, $src0",
[(set DReg:$dst, (OpNode SReg:$src0, timm:$src1))]>;
class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace = "AMDI...
2011 Sep 13
3
[LLVMdev] Setting priority in instruction selection
...eInOneOut<IL_OP_BFI, (outs GPRI32:$dst),
(ins GPRI32:$lhs, GPRI32:$rhs, GPRI32:$bitpat),
!strconcat(IL_OP_BFI.Text, " $dst, $lhs, $rhs, $bitpat"),
[(set GPRI32:$dst, (bfi_pat1 GPRI32:$lhs, GPRI32:$rhs, GPRI32:$bitpat))]>;
and also this instruction:
def LOADCONST_i32 : ILFormat<IL_OP_MOV, (outs GPRI32:$dst),
(ins i32imm:$val),
"mov $dst, $src",
[(set GPRI32:$dst, imm:$val)]>;
Now, what is happening with this code, (A & B) | (C & ~B), where B is an immedate and ~B is an inverse of it,
instead of getting
LOADCONST_i32 r0 B
BFI_i3...
2009 Apr 15
1
[LLVMdev] Tablegen question
...: In MACRO_DISTANCE_FAST_v2f32: Type inference contradiction
> found in node!
>
> I'm using the following test td file.
>
> This is generated with putting it in include and running the command
> Tablegen.exe -dag-isel -I. test.td
>
>
> The pattern in question is:
> ILFormat<(outs Dst:$dst), (ins Src:$src0, Src:$src1),
> ",($dst),($src0, $src1)",
> [(set Dst:$dst, (OpNode Src:$src0, Src:$src1))]
>
> As the intrinsic specifies, the two source register classes should be
> the same, however, Tablegen is somehow...
2011 Sep 13
0
[LLVMdev] Setting priority in instruction selection
...PRI32:$lhs, GPRI32:$rhs, GPRI32:$bitpat),
>
> !strconcat(IL_OP_BFI.Text, " $dst, $lhs, $rhs, $bitpat"),
>
> [(set GPRI32:$dst, (bfi_pat1 GPRI32:$lhs, GPRI32:$rhs,
> GPRI32:$bitpat))]>;
>
> and also this instruction:
>
>
>
> def LOADCONST_i32 : ILFormat<IL_OP_MOV, (outs GPRI32:$dst),
>
> (ins i32imm:$val),
>
> "mov $dst, $src",
>
> [(set GPRI32:$dst, imm:$val)]>;
>
>
>
>
>
> Now, what is happening with this code, (A & B) | (C & ~B), where B is an
> immedate and ~B is...
2011 Sep 13
1
[LLVMdev] Setting priority in instruction selection
...; > !strconcat(IL_OP_BFI.Text, " $dst, $lhs, $rhs, $bitpat"),
> >
> > [(set GPRI32:$dst, (bfi_pat1 GPRI32:$lhs, GPRI32:$rhs,
> > GPRI32:$bitpat))]>;
> >
> > and also this instruction:
> >
> >
> >
> > def LOADCONST_i32 : ILFormat<IL_OP_MOV, (outs GPRI32:$dst),
> >
> > (ins i32imm:$val),
> >
> > "mov $dst, $src",
> >
> > [(set GPRI32:$dst, imm:$val)]>;
> >
> >
> >
> >
> >
> > Now, what is happening with this code, (A &a...
2009 Apr 15
0
[LLVMdev] Tablegen question
...v2f32:$src0,
GPRV2F32:f32:$src1))
TableGen.exe: In MACRO_DISTANCE_FAST_v2f32: Type inference contradiction
found in node!
I'm using the following test td file.
This is generated with putting it in include and running the command
Tablegen.exe -dag-isel -I. test.td
The pattern in question is:
ILFormat<(outs Dst:$dst), (ins Src:$src0, Src:$src1),
",($dst),($src0, $src1)",
[(set Dst:$dst, (OpNode Src:$src0, Src:$src1))]
As the intrinsic specifies, the two source register classes should be
the same, however, Tablegen is somehow interpreting that it should be
f32 instead of v2f...
2009 Apr 15
3
[LLVMdev] Tablegen question
Oops. That was premature. I think your original question was on the
right track. TableGen distinguishes between known and "overloaded"
types (like "llvm_anyfloat_ty" in your example). The overloaded types
are numbered separately, and the argument to LLVMMatchType is an index
into these overloaded types, ignoring the known types. So, in your
case, the first