Displaying 2 results from an estimated 2 matches for "iigenload".
2012 Nov 06
0
[LLVMdev] Compiling for several operand memories
Have not gotten much further on this, I can so far only use one memory with
(for example)
def LDr1 : F1< (outs GenRegs:$dst), (ins GenRegs:$addr),
"ld*0* $dst, ($addr)",
[(set GenRegs:$dst, (load GenRegs:$addr))],IIGenLoad>;
and
def LDrr : F1< (outs GenRegs:$dst), (ins MEMrr:$addr),
"ld*0* $dst, ($addr)",
[(set GenRegs:$dst, (load ADDRrr:$addr))],IIGenLoad>;
What i want to do is to be able to also have these two:
def LDr1 : F1< (outs GenRegs:$dst), (...
2012 Oct 05
2
[LLVMdev] Compiling for several operand memories
Hello,
My target has two data memories, each with its own load/store instructions but also has some instructions using both memories. I want to be able to access both memories in C-programs through the address space attribute.
I have two ideas so far:
Either: use two sets of addressing modes in InstrInfo.td:
def ADDRrr_A : ComplexPattern<i16, 2, “SelectADDRrr_A", [], []>;
def ADDRri :