Displaying 5 results from an estimated 5 matches for "iic_ialui".
2016 Jun 06
2
Instruction Itineraries: question about operand latencies
...d and made all of the load numbers high, such as:
InstrItinData< II_LOAD1, [InstrStage<150, [AGU]>]>,
However, I see that there is another field which I haven't specified where
operand latencies are specified. Here's an example from
ARMScheduleA8.td:
InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
Now I'm wondering if Instead of what I had above, I should instead have
specified:
InstrItinData< II_LOAD1, [InstrStage<150, [AGU]>],[150,1,1]>,
?
but is that first '150' parameter there redundant? Since it&...
2016 Jun 08
2
Instruction Itineraries: question about operand latencies
...InstrItinData< II_LOAD1, [InstrStage<150, [AGU]>]>,
>>
>> However, I see that there is another field which I haven't specified
>> where operand latencies are specified. Here's an example from
>> ARMScheduleA8.td:
>>
>> InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
>>
>> Now I'm wondering if Instead of what I had above, I should instead have
>> specified:
>>
>> InstrItinData< II_LOAD1, [InstrStage<150, [AGU]>],[150,1,1]>,
>>
>> ?
>>...
2019 Apr 14
2
[A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM
...LLVM for thumb2 add. Probably starting with t2 instead of t.
The definition of tADDi8 looks like this. Where tGPR specifically means R0-R7.
def tADDi8 : // A8.6.4 T2
T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
(ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
"add", "\t$Rdn, $imm8",
[(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
Sched<[WriteALU]>;
~Craig
On Sun, Apr 14, 2019 at 12:21 PM Jie Zhou <jzhou41 at cs.rochester.edu<mailto:jzhou41 at cs....
2019 Apr 14
2
[A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM
Sorry for not being specific enough. ARMv7-M includes Thumb and Thumb2.
It has 12 regular registers (R0 - R12), and R8 - R12 are used.
I can generate mov instruction that from/ R8-R12 to/from R0-R6.
From this ARM page http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/ch03s03s01.html
R9 - R12 have their conventional usage, but I don’t if this is the reason we cannot
use them
2012 Aug 23
0
[LLVMdev] % in tablegen
...tried '\' character, and two "%%". None worked.
// ADD <Rd>, sp, #<imm8>
// This is rematerializable, which is particularly useful for taking the
// address of locals.
let isReMaterializable = 1 in
def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs),
IIC_iALUi,
"add\t$dst, %prefix_$sp, $rhs", []>,
T1Encoding<{1,0,1,0,1,?}> {
// A6.2 & A8.6.8
bits<3> dst;
bits<8> rhs;
let Inst{10-8} = dst;
let Inst{7-0} = rhs;
}
- Khaled
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