search for: ii32

Displaying 11 results from an estimated 11 matches for "ii32".

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2005 May 06
2
[LLVMdev] initialize 'dag' variable and interpret asmstring in tablegen .td file
llvm/lib/Target/X86/X86InstrInfo.td: class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> : Instruction { .... dag OperandList = ops; string AsmString = AsmStr; } def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), "mov{l} {$src, $dst|$dst, $src}">; I cannot find any document on initializing the 'dag' type variable, and I cannot understand the syntax of "asmstring" either. how does the x86 asmwrite interpret th...
2013 Nov 27
0
[LLVMdev] Some bugs in x86 disasm (llvm-mc)
Hi Jun, I'm not sure how to fix this yet, but this looks incorrectly defined in lib/Target/X86/X86InstrInfo.td: def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src), "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, Requires<[In32BitMode]>; This instruction can be REX-prefixed for a 64-bit move, and that also doesn't appear to be defined anywhere....
2005 May 06
0
[LLVMdev] initialize 'dag' variable and interpret asmstring in tablegen .td file
...6 May 2005, Tzu-Chien Chiu wrote: > llvm/lib/Target/X86/X86InstrInfo.td: > class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string > AsmStr> : Instruction { > .... > dag OperandList = ops; > string AsmString = AsmStr; > } > > def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), > "mov{l} {$src, $dst|$dst, $src}">; > > I cannot find any document on initializing the 'dag' type variable, > and I cannot understand the syntax of "asmstring" either. The DAG operator is...
2007 Sep 11
0
[LLVMdev] RFC: Tail call optimization X86
...5. +// the following two instructions are used to adjust the stack pointer +// in the case where the callee has more arguments than the caller +// an area is created where the return addr can be safely moved to +let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. +def TCADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst), (ins GR32: $src1, i32imm:$src2), + "add{l}\t{$src2, $dst|$dst, $src2}", + []>; +} + +def TCSUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32: $src1, i32imm:$src2), + "sub{l}\t{$s...
2005 May 06
1
[LLVMdev] initialize 'dag' variable and interpret asmstring in tablegen .td file
...llvm/lib/Target/X86/X86InstrInfo.td: > > class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string > > AsmStr> : Instruction { > > .... > > dag OperandList = ops; > > string AsmString = AsmStr; > > } > > > > def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), > > "mov{l} {$src, $dst|$dst, $src}">; > > > > I cannot find any document on initializing the 'dag' type variable, > > and I cannot understand the syntax of "asmstring" either. &...
2013 Nov 27
3
[LLVMdev] Some bugs in x86 disasm (llvm-mc)
Hi, With objdump, i have this (Intel syntax) 64 a1 00 00 00 00 mov eax,fs:0x0 However, if I pass above string to llvm-mc, I would have: $ echo "0x64 0xa1 0x00 0x00 0x00 0x00"|./Release+Asserts/bin/llvm-mc -disassemble -arch=x86 --output-asm-variant=1 .text mov eax, dword ptr [0] You can see a big difference. This is on the latest code. Any idea how to
2018 Mar 28
0
x86 instruction format which takes a single 64-bit immediate
Copy Ii32 in X86InstrFormats.td rename to Ii64 and change Imm32 to Imm64. Instantiate your instruction inheriting from Ii64. Pass RawFrm to the form parameter. Initial documentation for the encoding system is attached. ~Craig On Wed, Mar 28, 2018 at 4:50 PM, Gus Smith via llvm-dev < llvm-dev at lists.l...
2014 Jan 14
2
[LLVMdev] Some bugs in x86 disasm (llvm-mc)
On Thu, Nov 28, 2013 at 1:03 AM, Kay Tiong Khoo <kkhoo at perfwizard.com>wrote: > Hi Jun, > > I'm not sure how to fix this yet, but this looks incorrectly defined in > lib/Target/X86/X86InstrInfo.td: > > def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src), > "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, > Requires<[In32BitMode]>; > > This instruction can be REX-prefixed for a 64-bit move, and that also > doesn't appear...
2018 Mar 28
4
x86 instruction format which takes a single 64-bit immediate
I am attempting to create an instruction which takes a single 64-bit immediate. This doesn't seem like a thing that would exist already (because who needs an instruction which just takes an immediate?) How might I implement this easily? Perhaps I could use a format which encodes a register, which is then unused? Thanks for the help. Gus -------------- next part -------------- An HTML
2007 Sep 06
2
[LLVMdev] RFC: Tail call optimization X86
Hi Evan, first off thanks to you and Chris for taking time. On 6 Sep 2007, at 00:57, Evan Cheng wrote: > We'd like to see tail call optimization to be similar to the target > independent lowering of ISD::CALL nodes. These are auto-generated > from ???CallingConv.td files. Some target specific details such as > function address register (ECX in your example) should be coded in
2007 Sep 11
2
[LLVMdev] RFC: Tail call optimization X86
...structions are used to adjust the stack > pointer > +// in the case where the callee has more arguments than the caller > +// an area is created where the return addr can be safely moved to > +let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. > +def TCADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst), (ins GR32: > $src1, i32imm:$src2), > + "add{l}\t{$src2, $dst|$dst, $src2}", > + []>; > +} > + > +def TCSUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32: > $src1, i32imm:$src2), >...