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...gets converted in my back end's machine instrution VLOAD_D, although the custom code seems to always select instructions in a valid way.) ******** Pre-regalloc Machine LICM: Test ******** Entering BB#4 Hoist non-reg-pressure: %vreg50<def> = VLOAD_D 1; MSA128D:%vreg50 dbg:IfVectorize.c:37:16 Hoisting %vreg50<def> = VLOAD_D 1; MSA128D:%vreg50 dbg:IfVectorize.c:37:16 from BB#4 to BB#3 Hoist non-reg-pressure: %vreg51<def> = VLOAD_D 0; MSA128D:%vreg51 Hoisting %vreg51<def> = VLOAD_D 0; MSA128D:%vreg51 from BB#4 to BB#3 Can't...

...r at compilation (at scheduling): BB#0: derived from LLVM BB %entry Live Ins: %R1 %R2 %vreg6<def> = COPY %R2; GPR:%vreg6 %vreg5<def> = COPY %R1; GPR:%vreg5 %vreg12<def> = VLOAD_D_WO_IMM; MSA128D:%vreg12 dbg:IfVectorize.c:39:5 INLINEASM <es: (Param1 - Param2); // MSA_I10> [sideeffect] [attdialect], <llc: /llvm/include/llvm/Support/Casting.h:237: typename llvm::cast_retty<X, Y*>::ret_type llvm::cast(Y*) [with X = llvm::ValueAsMetadata; Y = const llvm::Metadata; typename llv...