search for: isvector

...ctor(x) [1] T S> names(x) <- letters[1:5] S> is.vector(x) [1] F Essentially, everything in S is a vector unless it has attributes. This is utterly unreasonable! Why should something stop being a vector because it has a names attribute attached. Internally in R, we have a predicate isVector() which returns true if its argument has one of the storage modes "logical", "factor", "ordered", "integer", "real", "complex" and "character". This is useful because these are the types which can be subscripted (without using C...

...else if(isInteger(colData)) i = INTEGER(colData)[j]; else if(isString(colData)) s = CHAR(STRING_ELT(colData,j)) The problem is that the last test (isString) never passes, even when I pass in a frame for which one or more cols contain character strings. When the column contains strings the isVector(colData) test passes, but no matter how I try to fetch the string data I get a seg fault. That is, forcing CHAR(STRING_ELT(colData,j)) will fault, and so will VECTOR_ELT(colData,0), even though colData passes the isVector test. Any ideas? Thanks, ds

Consider the R code: mat <- matrix(seq(1,20),4,5) is.matrix(mat) # gives TRUE is.vector(mat) # gives FALSE On the other hand, if mat is passed through the .Call interface the corresponding SEXP (call it smat) satisfies isMatrix(smat) // TRUE isVector(smat) // TRUE Consequently, you cannot distinguish matrices from vectors. Looking at the dim attribute of a vector doesn't help because this is garbage. Dominick

...(MVT::ValueType)VT, Promote); > AddPromotedToType (ISD::AND, (MVT::ValueType)VT, > MVT::v2i64); > ... > > Evan Thanks Evan, I had tried something like this, but ran into some problems. llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1478: failed assertion `MVT::isVector(VT) && "Cannot promote this load!"' and llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1766: failed assertion `MVT::isVector(VT) && "Unknown legal promote case!"' it appears that for load/store only vector types of equivalent bit- widths can be prom...

...+++ b/lib/Target/X86/X86ISelLowering.cpp > @@ -4837,6 +4837,11 @@ bool X86TargetLowering::isCheapToSpeculateCtlz() > const { > > bool X86TargetLowering::isLoadBitCastBeneficial(EVT LoadVT, > EVT BitcastVT) const { > + if (!LoadVT.isVector() && BitcastVT.isVector() && > + BitcastVT.getVectorElementType() == MVT::i1 && > + !Subtarget.hasAVX512()) > + return false; > + > if (!Subtarget.hasDQI() && BitcastVT == MVT::v8i1) > return false; > > > ~Craig > &g...

...i8. When we visit the SIGN_EXTEND, we generate the ISD::SELECT even though the selector and both operands are vectors. It sounds like a bug in the dag combine optimization. If you send me the line number I will take a look. Line 4501 in trunk DAGCombiner.cpp… I changed the ISD::SELECT to the VT.isVector() ? ISD::VSELECT : ISD::SELECT... We should probably add an assert in SelectionDAG::getNode(). I've tried a local change that cures this particular assert, but uncovers another assert later, so I'm a bit uncertain if I'm heading off in the wrong direction. Adding assertions to getNo...

> > Thanks Evan, > > I had tried something like this, but ran into some problems. > > llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1478: failed assertion > `MVT::isVector(VT) && "Cannot promote this load!"' > > and > > llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1766: failed assertion > `MVT::isVector(VT) && "Unknown legal promote case!"' > > > it appears that for load/store only vector types of e...

...&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;TypeSetByHwMode &amp;Big) { Small-&gt;dump(); //{ *:[i16] } Big-&gt;dump(); //&nbsp;{ *:[v1i32] } .... &nbsp; &nbsp; if (none_of(S, isVector) || none_of(B, isVector)) { &nbsp; &nbsp; &nbsp; Changed |= berase_if(S, isVector) | &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;berase_if(B, isVector); &nbsp; &nbsp; } Changed turn to True here which trigger the final error...

Here's a reworked patch to mark instructions and operands as vector or scalar. It uses TableGen to infer the flags from types, allowing the user to override with a "let isVector = 0" clause. I decided to forego classifying MachineMemOperands for now in the interests of getting this piece in. I still think we should add type information to MachineMemOperands. Why throw away perfectly good information we have at the time they're created? Obviously I will submit...

What is the proper solution to disable auto-vectorization for unaligned data? I have an out of tree target and I added this: bool OpusTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { if (VT.isVector()) return false; .... } After that, I could see that vectorization is still done on unaligned data except that llvm will copy the data back and forth from the source to the top of the stack and work from there. This is very costly, I rather get scalar operations. Then I tried to add: unsign...

Full_Name: Antonio Possolo Version: 1.3.1 OS: Linux (RH 7.1), Windows 2000 Submission from: (NULL) (192.35.44.3) A FEATURE THAT EASILY GENERATES BUGS sample(pi, size=1) produces 1, 2, or 3. sample(c(pi, pi), size=1) produces 3.141593 always. Although this conforms with the behavior explained in the help page for "sample", the behavior for the case where x (in sample(x, ...)) has

Hi all, I've run into a case where the optimizer seems to be having trouble doing the "obvious" thing. Consider this code: ``` define i16 @foo(<8 x i16>* dereferenceable(16) %egress, <16 x i8> %a0) { %a1 = icmp slt <16 x i8> %a0, zeroinitializer %a2 = bitcast <16 x i1> %a1 to i16 %astore = getelementptr inbounds <8 x i16>, <8 x i16>*

> > Line 4501 in trunk DAGCombiner.cpp… I changed the ISD::SELECT to the VT.isVector() ? ISD::VSELECT : ISD::SELECT... > Thanks. From the commit message I think that we should only run this optimization on scalars. >> Can you write down the input SDNode ? What types are inputs ? > > 0x107046d10: v2i8 = vselect 0x107046c10, 0x107046b10, 0x107045e10 [I...

...org/pipermail/llvm-dev/2016-April/098823.html I'm still trying to compile a library with clang. But now I'm getting as assert in lib/CodeGen/TargetLoweringBase.cpp:1155: virtual llvm::EVT llvm::TargetLoweringBase::getSetCCResultType(llvm::LLVMContext&, llvm::EVT) const: Assertion `!VT.isVector() && "No default SetCC type for vectors!"' failed. I'm still learning LLVM, but unfortunately I don't know what this assert could be related to. I would really appreciate any input on this. I'm running clang-3.5. For now I'm stuck with this version. If you ne...

...probably add an assert in SelectionDAG::getNode(). I've tried a local change that cures this particular assert, but uncovers another assert later, so I'm a bit uncertain if I'm heading off in the wrong direction. I think that replacing SELECT with VSELECT is the right thing to do. VT.isVector() ? ISD::VSELECT : ISD::SELECT in lieu of the fixed ISD::SELECT seems to do the trick for me. Except that it sometimes hits the assert in ExpandVSELECT... The subsequent assert comes in ExpandVSELECT, which expects (for no good reason as far as I can tell) that the "mask" (really the ...

In 2.8.0/Windows Vista: When 'unique' gives a type error message, it prints out even if errors are being caught: > try(unique(quote(hello)),silent=TRUE) hello This comes from the .Internal unique routine: > try(.Internal(unique(quote(hello),NULL,NULL)),silent=TRUE) hello I guess it is using the internal equivalent of print rather than the internal equivalent of stop.

I'm working on version 2.0 The assertion at line 2380 of LegalizeDAG.cpp fails when it is trying to lower the add with i16. assertion reads: assert(MVT::isVector(Node->getValueType(0)) && "Cannot expand this binary operation!"); I am trying to compile a very simple program as follows: short var; void foo(void) { Var++; } The input bytecode, (in addition to the debug stuff) contains: %tmp = load i16* @var ;<i16> [#u...

...tain if I'm heading off in the wrong direction. >> Adding assertions to getNode is the right thing to do. I am not sure that it will solve your problem, but it will help us some some problems. >> I think that replacing SELECT with VSELECT is the right thing to do. > > VT.isVector() ? ISD::VSELECT : ISD::SELECT in lieu of the fixed ISD::SELECT seems to do the trick for me. Except that it sometimes hits the assert in ExpandVSELECT… Okay. Which assertion in ExpandVSELECT fail ? Maybe our assumptions there are incorrect. > >>> The subsequent assert comes in Exp...

...amp;nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;TypeSetByHwMode &amp;Big) { Small-&gt;dump(); //{ *:[i16] } Big-&gt;dump(); // { *:[v1i32] } .... &nbsp; &nbsp; if (none_of(S, isVector) || none_of(B, isVector)) { &nbsp; &nbsp; &nbsp; Changed |= berase_if(S, isVector) | &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;berase_if(B, isVector); &nbsp; &nbsp; } Changed turn to True here which tr...

...gnTopologicalOrder(); + for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), + E = prior(DAG.allnodes_end()); I != next(E); ++I) { + bool HasVectorValue = false; + for (SDNode::value_iterator J = I->value_begin(); J != I->value_end(); ++J) + HasVectorValue |= J->isVector(); + if (!HasVectorValue) continue; + SDNode* Result = I; + switch (I->getOpcode()) { + default: + assert(I->getOpcode() > ISD::BUILTIN_OP_END && "Unexpected node!"); + break; + case ISD::UNDEF: + case ISD::FORMAL_ARGUMENTS: + case ISD::CALL...