search for: idtr

...2 app. Here is what I have tried: void int3_handler() { put_str("int3!!!"); __asm__("iret"); } void init_handlers() { struct { unsigned long limit : 16; unsigned long base : 32; } __attribute__((packed)) idtr; __asm__("sidt (%0)" :: "r"(&idtr)); unsigned long *idt = (void*)idtr.base; idt[3] = int3_handler; put_str("about to try int3"); anykey(); __asm__("sti"); __asm__("int3"); put_s...

...is patch is fine. I have a couple of nit-picking comments: > + if (target_mask&0x1) { The formatting here isn't quite what most of the kernel does. It would be better if you added spaces so it's a little easier to read, ie: if (target_mask & 0x1) { > + p = &__per_cpu_idtrs[cpu][0][0]; > + for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, > cpu); > + i++, > p++) { > + if (p->pte&0x1) Same thing here. > +#define RR_TO_RID(rr) ((rr)<<32>>40) I would prefer to have this one defined like this: #define RR_TO_RID(...

...is patch is fine. I have a couple of nit-picking comments: > + if (target_mask&0x1) { The formatting here isn't quite what most of the kernel does. It would be better if you added spaces so it's a little easier to read, ie: if (target_mask & 0x1) { > + p = &__per_cpu_idtrs[cpu][0][0]; > + for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, > cpu); > + i++, > p++) { > + if (p->pte&0x1) Same thing here. > +#define RR_TO_RID(rr) ((rr)<<32>>40) I would prefer to have this one defined like this: #define RR_TO_RID(...

...0000000000000000, CR3 - 000000001FC01000 CR4 - 0000000000000668, CR8 - 0000000000000000 DR0 - 0000000000000000, DR1 - 0000000000000000, DR2 - 0000000000000000 DR3 - 0000000000000000, DR6 - 00000000FFFF0FF0, DR7 - 0000000000000400 GDTR - 000000001FBEEA98 0000000000000047, LDTR - 0000000000000000 IDTR - 000000001F6A9018 0000000000000FFF, TR - 0000000000000000 FXSAVE_STATE - 000000001FF13310 select help: !!!! X64 Exception Type - 0D(#GP - General Protection) CPU Apic ID - 00000000 !!!! ExceptionData - 0000000000000000 RIP - AFAFAFAFAFAFAFAF, CS - 0000000000000038, RFLAGS - 0000000000000286...

> ah ha... now that I have all the pices in place, this is what I was missing: > > # EFI/BOOT/SYSLX64.CFG > # D-I config version 2.0 > # search path for the c32 support libraries (libcom32, libutil etc.) > PATH EFI/BOOT/SYSLINUX/EFI64/ > DEFAULT common > PROMPT 0 > LABEL common > CONFIG ../../syslinux.cfg ../../ > > The syslinux.cfg and all the other .cfg

ioemu-remote: The device model needs to write in the ACPI tables when it wakes up from S3 state. Signed-off-by: Jean Guyader <jean.guyader@eu.citrix.com> -- Jean Guyader _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

...the traditional init/startup + IPI sequence, the BSP must issue the init IPI, a set application + processor state hypercall, followed by the startup IPI. + + The initial state contains the AP's control registers, general + purpose registers and segment registers, as well as the IDTR, + GDTR, LDTR and EFER. Any processor state not included in the initial + AP state (including x87 FPRs, SSE register states, and MSRs other than + EFER), are left in the poweron state. + + The BSP must construct the initial GDT used by each AP. The segment + register hidden s...

...the traditional init/startup + IPI sequence, the BSP must issue the init IPI, a set application + processor state hypercall, followed by the startup IPI. + + The initial state contains the AP's control registers, general + purpose registers and segment registers, as well as the IDTR, + GDTR, LDTR and EFER. Any processor state not included in the initial + AP state (including x87 FPRs, SSE register states, and MSRs other than + EFER), are left in the poweron state. + + The BSP must construct the initial GDT used by each AP. The segment + register hidden s...

...attr=0x1c000, limit=0xffffffff, base=0x0000000000000000 (XEN) GS: sel=0x0000, attr=0x1c000, limit=0xffffffff, base=0xffff880078800000 (XEN) GDTR: limit=0x0000007f, base=0xffff880078804000 (XEN) LDTR: sel=0x0000, attr=0x1c000, limit=0xffffffff, base=0x0000000000000000 (XEN) IDTR: limit=0x00000fff, base=0xffffffff81bb7000 (XEN) TR: sel=0x0040, attr=0x0008b, limit=0x00002087, base=0xffff880078811440 (XEN) Guest PAT = 0x0007010600070106 (XEN) TSC Offset = ffffff7bb9c04f5e (XEN) DebugCtl=0000000000000000 DebugExceptions=0000000000000000 (XEN) Interrup...

I have installed paltalk (chatting client) and it is working properly when it comes to hearing and talking. However, whenever I try to write, if I type one word no speace like "hello" i will have no problem. But if I was to type two words with as much as single space like "hello world" paltalk gives me the error below: Code: Alert: Your last text message was not sent because

The KVM introspection subsystem provides a facility for applications running on the host or in a separate VM, to control the execution of other VMs (pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.), alter the page access bits in the shadow page tables (only for the hardware backed ones, eg. Intel's EPT) and receive notifications when events of interest have taken place

The KVM introspection subsystem provides a facility for applications running on the host or in a separate VM, to control the execution of other VMs (pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.), alter the page access bits in the shadow page tables (only for the hardware backed ones, eg. Intel's EPT) and receive notifications when events of interest have taken place

The KVM introspection subsystem provides a facility for applications running on the host or in a separate VM, to control the execution of other VM-s (pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.), alter the page access bits in the shadow page tables (only for the hardware backed ones, eg. Intel's EPT) and receive notifications when events of interest have taken place

The KVM introspection subsystem provides a facility for applications running on the host or in a separate VM, to control the execution of other VM-s (pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.), alter the page access bits in the shadow page tables (only for the hardware backed ones, eg. Intel's EPT) and receive notifications when events of interest have taken place