search for: dtr

...ine load_LDT_desc() __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8)) +#define load_TR_desc() asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)) +#define load_LDT_desc() asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8)) -#define load_gdt(dtr) __asm__ __volatile("lgdt %0"::"m" (*dtr)) -#define load_idt(dtr) __asm__ __volatile("lidt %0"::"m" (*dtr)) -#define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr)) -#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"m...

...ine load_LDT_desc() __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8)) +#define load_TR_desc() asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)) +#define load_LDT_desc() asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8)) -#define load_gdt(dtr) __asm__ __volatile("lgdt %0"::"m" (*dtr)) -#define load_idt(dtr) __asm__ __volatile("lidt %0"::"m" (*dtr)) -#define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr)) -#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"m...

...ine load_LDT_desc() __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8)) +#define load_TR_desc() asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)) +#define load_LDT_desc() asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8)) -#define load_gdt(dtr) __asm__ __volatile("lgdt %0"::"m" (*dtr)) -#define load_idt(dtr) __asm__ __volatile("lidt %0"::"m" (*dtr)) -#define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr)) -#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"m...

...ine load_LDT_desc() __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8)) +#define load_TR_desc() asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)) +#define load_LDT_desc() asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8)) -#define load_gdt(dtr) __asm__ __volatile("lgdt %0"::"m" (*dtr)) -#define load_idt(dtr) __asm__ __volatile("lidt %0"::"m" (*dtr)) -#define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr)) -#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"m...

...-0700 @@ -33,19 +33,6 @@ extern struct Xgt_desc_struct idt_descr, cpu_gdt_descr[NR_CPUS]; -#define load_TR_desc() asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)) -#define load_LDT_desc() asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8)) - -#define load_gdt(dtr) asm volatile("lgdtl %0"::"m" (*dtr)) -#define load_idt(dtr) asm volatile("lidtl %0"::"m" (*dtr)) -#define load_tr(tr) asm volatile("ltr %0"::"mr" (tr)) -#define load_ldt(ldt) asm volatile("lldt %0"::"mr" (ldt)) - -#def...

...-0700 @@ -33,19 +33,6 @@ extern struct Xgt_desc_struct idt_descr, cpu_gdt_descr[NR_CPUS]; -#define load_TR_desc() asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)) -#define load_LDT_desc() asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8)) - -#define load_gdt(dtr) asm volatile("lgdtl %0"::"m" (*dtr)) -#define load_idt(dtr) asm volatile("lidtl %0"::"m" (*dtr)) -#define load_tr(tr) asm volatile("ltr %0"::"mr" (tr)) -#define load_ldt(ldt) asm volatile("lldt %0"::"mr" (ldt)) - -#def...

...get_cp return (struct desc_struct *)per_cpu(cpu_gdt_descr, cpu).address; } -#define load_TR_desc() __asm__ __volatile__("ltr %w0"::"q" (GDT_ENTRY_TSS*8)) -#define load_LDT_desc() __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8)) - -#define load_gdt(dtr) __asm__ __volatile("lgdt %0"::"m" (*dtr)) -#define load_idt(dtr) __asm__ __volatile("lidt %0"::"m" (*dtr)) -#define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr)) -#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"m...

...get_cp return (struct desc_struct *)per_cpu(cpu_gdt_descr, cpu).address; } -#define load_TR_desc() __asm__ __volatile__("ltr %w0"::"q" (GDT_ENTRY_TSS*8)) -#define load_LDT_desc() __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8)) - -#define load_gdt(dtr) __asm__ __volatile("lgdt %0"::"m" (*dtr)) -#define load_idt(dtr) __asm__ __volatile("lidt %0"::"m" (*dtr)) -#define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr)) -#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"m...

Hi, this is a series of patches that unify the struct desc_struct and friends across x86_64 and i386. As usual, it provides paravirt capabilities as a side-effect for x86_64. I consider the main goal, namely, of unifying the desc_struct, an ongoing effort, being this the beginning. A lot of old code has to be touched to accomplish that. I don't consider this patch ready for inclusion.

Hi, this is a series of patches that unify the struct desc_struct and friends across x86_64 and i386. As usual, it provides paravirt capabilities as a side-effect for x86_64. I consider the main goal, namely, of unifying the desc_struct, an ongoing effort, being this the beginning. A lot of old code has to be touched to accomplish that. I don't consider this patch ready for inclusion.

...d Deltec PowerRite Pro 2 UPS which has a 9 pin serial cable. By trial and error Im pretty sure I found LB = DCD, but can not get the combination for OB / OL. No matter what I do I get the results below. driver.name: genericups driver.parameter.CP: CTS driver.parameter.LB: DCD driver.parameter.OL: DTR driver.parameter.SD: DTR+RTS driver.parameter.upstype: 21 driver.version: 2.0.2 driver.version.internal: 1.30 ups.mfr: Generic ups.model: Generic RUPS 2000 ups.status: OB Anyone happen to have some hints as to what the correct settings might be ? Thanks again Martin

...t; >If you have a multimeter, you could check pin 9 on the UPS relative to pin 4/7 to see if it is being driven negative. I mesured it and on DC and it shows 0 V (zero V). May be the information (pls. see attachment) that UPS PIN1 should bee keept HI is mandatory. Should I connect it to PC PIN4 DTR? OR I need to follow with contact closure cable? Best regards, Robert SZAKSZ. -------------- next part -------------- A non-text attachment was scrubbed... Name: Infosec_UPS_connector.PNG Type: image/png Size: 51305 bytes Desc: not available URL: <http://lists.alioth.debian.org/pipermail/nu...

.../x86/include/asm/desc.h index d0a21b12dd58..f6630e73843c 100644 --- a/arch/x86/include/asm/desc.h +++ b/arch/x86/include/asm/desc.h @@ -128,7 +128,6 @@ static inline int desc_empty(const void *ptr) #define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt)) #define store_gdt(dtr) native_store_gdt(dtr) -#define store_idt(dtr) native_store_idt(dtr) #define store_tr(tr) (tr = native_store_tr()) #define load_TLS(t, cpu) native_load_tls(t, cpu) @@ -248,7 +247,7 @@ static inline void native_store_gdt(struct desc_ptr *dtr) asm volatile("sgdt %0":"=...

.../x86/include/asm/desc.h index d0a21b12dd58..f6630e73843c 100644 --- a/arch/x86/include/asm/desc.h +++ b/arch/x86/include/asm/desc.h @@ -128,7 +128,6 @@ static inline int desc_empty(const void *ptr) #define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt)) #define store_gdt(dtr) native_store_gdt(dtr) -#define store_idt(dtr) native_store_idt(dtr) #define store_tr(tr) (tr = native_store_tr()) #define load_TLS(t, cpu) native_load_tls(t, cpu) @@ -248,7 +247,7 @@ static inline void native_store_gdt(struct desc_ptr *dtr) asm volatile("sgdt %0":"=...

(Andrew, please sit these in the -mm tree for cooking) Create a paravirt.h header for (almost) all the critical operations which need to be replaced with hypervisor calls. For the moment, this simply includes no_paravirt.h, where all the native implementations now live. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Zachary Amsden <zach@vmware.com>

(Andrew, please sit these in the -mm tree for cooking) Create a paravirt.h header for (almost) all the critical operations which need to be replaced with hypervisor calls. For the moment, this simply includes no_paravirt.h, where all the native implementations now live. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Zachary Amsden <zach@vmware.com>

...esc(void) +{ + __asm__ __volatile__("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); +} + +static fastcall void nopara_load_ldt_desc(void) +{ + __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8)); +} + +static fastcall void nopara_load_gdt(const struct Xgt_desc_struct *dtr) +{ + __asm__ __volatile("lgdt %0"::"m" (*dtr)); +} + +static fastcall void nopara_load_idt(const struct Xgt_desc_struct *dtr) +{ + __asm__ __volatile("lidt %0"::"m" (*dtr)); +} + +static fastcall void nopara_store_gdt(struct Xgt_desc_struct *dtr) +{ + __asm_...

...esc(void) +{ + __asm__ __volatile__("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); +} + +static fastcall void nopara_load_ldt_desc(void) +{ + __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8)); +} + +static fastcall void nopara_load_gdt(const struct Xgt_desc_struct *dtr) +{ + __asm__ __volatile("lgdt %0"::"m" (*dtr)); +} + +static fastcall void nopara_load_idt(const struct Xgt_desc_struct *dtr) +{ + __asm__ __volatile("lidt %0"::"m" (*dtr)); +} + +static fastcall void nopara_store_gdt(struct Xgt_desc_struct *dtr) +{ + __asm_...

...connection was okay, I hunted around on the net and found the following document: http://ftp.nluug.nl/os/Linux/distr/smeserver/contribs/rmitchell/smeserver/howto/powstatd HOWTO for sme server.htm It indicates that the settings to use when connected via a INT-0025C are: init0 dsr init0 rng init0 dtr init1 rts fail cts,0 low dcd,0 kill dtr,1 This seems to agree with the definition of type 7 in genericups.h: /* Type 7 */ { "CyberPower", "Power99", "CyberPower Power99", TIOCM_RTS, /* cable power: RTS */ TIOCM_CTS, TIOCM_CTS, /* online: CTS on */ TIO...

...from the manufacturer of my ups Kobian/Mercury and were tested wtih powstatd on Linux (Works OK). Now i want to configure it with NUT and i didn't have any luck (it always says OB) Initiliasation for monitoring: RTS = 1 (High) Main power fail: CTS = 0 (Low) Batter low: DCD = 0 (Low) Kill UPS: DTR = 0 (Low) How would the ups.conf look like? Reagards, Lep pozdrav, Markelj Toma?