Displaying 9 results from an estimated 9 matches for "i96".
Did you mean:
496
2010 Jan 29
2
[LLVMdev] 64bit MRV problem: { float, float, float} -> { double, float }
...);
}
llvm-gcc -c -emit-llvm -O3 produces this:
%struct.float3 = type { float, float, float }
define void @test(double %a.0, float %a.1, %struct.float3* nocapture
%res) nounwind noinline {
entry:
%tmp8 = bitcast double %a.0 to i64 ; <i64> [#uses=1]
%tmp9 = zext i64 %tmp8 to i96 ; <i96> [#uses=1]
%tmp1 = lshr i96 %tmp9, 32 ; <i96> [#uses=1]
%tmp2 = trunc i96 %tmp1 to i32 ; <i32> [#uses=1]
%tmp3 = bitcast i32 %tmp2 to float ; <float> [#uses=1]
%0 = getelementptr inbounds %st...
2010 Jan 29
0
[LLVMdev] 64bit MRV problem: { float, float, float} -> { double, float }
...roduces this:
>
> %struct.float3 = type { float, float, float }
> define void @test(double %a.0, float %a.1, %struct.float3* nocapture
> %res) nounwind noinline {
> entry:
> %tmp8 = bitcast double %a.0 to i64 ; <i64> [#uses=1]
> %tmp9 = zext i64 %tmp8 to i96 ; <i96> [#uses=1]
> %tmp1 = lshr i96 %tmp9, 32 ; <i96> [#uses=1]
> %tmp2 = trunc i96 %tmp1 to i32 ; <i32> [#uses=1]
> %tmp3 = bitcast i32 %tmp2 to float ; <float> [#uses=1]
> %0 = getele...
2010 Jan 25
0
[LLVMdev] 64bit MRV problem: { float, float, float} -> { double, float }
Hi Ralf,
> I do not understand why this behaviour is required. What is the problem
> in having a function receive a single struct-parameter with three floats
> compared to two scalar parameters?
>
> source-code (C++):
> struct Test3Float { float a, b, c; };
> void test(Test3Float param, Test3Float* result) { ... }
if you compile this with GCC, you will see that it too
2010 Jan 25
2
[LLVMdev] 64bit MRV problem: { float, float, float} -> { double, float }
Uh, sorry, did not pay attention where I was replying ;)
Hey Duncan,
I do not understand why this behaviour is required. What is the problem
in having a function receive a single struct-parameter with three floats
compared to two scalar parameters?
source-code (C++):
struct Test3Float { float a, b, c; };
void test(Test3Float param, Test3Float* result) { ... }
bitcode:
2019 Nov 28
3
Instcombine and bitcast of vector. Wrong CHECKs in cast.ll, miscompile in instcombine?
...%call4) {
; CHECK-LABEL: @test60(
; CHECK-NEXT: [[P10:%.*]] = shufflevector <4 x i32> [[CALL4:%.*]],
<4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
; CHECK-NEXT: ret <3 x i32> [[P10]]
;
%p11 = bitcast <4 x i32> %call4 to i128
%p9 = trunc i128 %p11 to i96
%p10 = bitcast i96 %p9 to <3 x i32>
ret <3 x i32> %p10
}
If we assume the input vector is e.g. <1, 2, 3, 4> then I assume %p11
would be the (hex) value 1234, %p9 would be the 234 and %p10 would then
be the vector <2, 3, 4>.
Am I right, or am I missing something here?...
2016 Sep 27
2
SelectionDAG::LegalizeTypes is very slow in 3.1 version
In 3.1, the backend is very slow to legalize types.
Following is the code snippet which may be the culprit:
%Result.i.i.i97 = alloca i33, align 8
%Result.i.i.i96= alloca i33, align 8
%Result.i.i.i95 = alloca i33, align 8
%Result.i.i.i94 = alloca i33, align 8
%Result.i.i.i93 = alloca i33, align 8
%Result.i.i.i92= alloca i33, align 8
%Result.i.i.i91 = alloca i33, align 8
%Result.i.i.i90 = alloca i33, align 8
%Result.i.i.i89 = alloca i33, align 8...
2013 Jan 27
0
[LLVMdev] SHL_PARTS and company
...fts to higher widths than the target would normally support. For
example, a 64-bit shift on a system with only 32-bit shift instructions. If
that is exactly the case, then I am a bit confused as to how one is
expected to implement even bit shifts on larger types that might appear in
IR, such as for i96, i128, or i256.
You could indeed handle i128 by doing Custom lowering on that operation via
setOperationAction with MVT::i64, but for sizes beyond that I don't see how
it could be accomplished without modifying CodeGen. Now, I'm not saying
that those types of large shifts are at likely to...
2013 Feb 14
1
[LLVMdev] LiveIntervals analysis problem
...2 %or.i91 to i16
br label %if.end.i102
if.end.i102: ; preds = %if.then.i93, %for.body.i89
%bits.1.i94 = phi i16 [ %conv2.i92, %if.then.i93 ], [ %bits.024.i86, %for.body.i89 ]
%conv3.i = zext i16 %13 to i32
%shl.i95 = shl nuw nsw i32 %conv3.i, 1
%conv5.i96 = zext i16 %bits.1.i94 to i32
%and6.i97 = lshr i32 %conv5.i96, 1
%and6.lobit.i = and i32 %and6.i97, 1
%storemerge.in.i = or i32 %and6.lobit.i, %shl.i95
%storemerge.i98 = trunc i32 %storemerge.in.i to i16
store i16 %storemerge.i98, i16* %x.addr.023.i87, align 2
%exitcond.i101 = icmp eq i...
2008 Jun 30
4
Rebuild of kernel 2.6.9-67.0.20.EL failure
Hello list.
I'm trying to rebuild the 2.6.9.67.0.20.EL kernel, but it fails even without
modifications.
How did I try it?
Created a (non-root) build environment (not a mock )
Installed the kernel.scr.rpm and did a
rpmbuild -ba --target=`uname -m` kernel-2.6.spec 2> prep-err.log | tee
prep-out.log
The build failed at the end:
Processing files: kernel-xenU-devel-2.6.9-67.0.20.EL
Checking