search for: i8imm

Hi Tom, Thanks. It should be always ABC. What should be the iops? just (ins i8imm:$val)? what would be the placeholder for a constant string in "ins"? On Thu, Nov 5, 2015 at 4:33 PM, Tom Stellard <tom at stellard.net> wrote: > On Thu, Nov 05, 2015 at 03:20:45PM +0100, Sky Flyer via llvm-dev wrote: > > Hello all, > > > > how can one can de...

...;xyz" is the operator, 14 is an immediate value, and because of assembly dialect, there should be a constant string with the value of ABC follow the immediate value. How is this possible? What should be the dat describing the instruction? string asm = "xyz $val ABC" dag iops = (ins i8imm:val, ... ) Cheers, ES -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20151105/3943fea5/attachment.html>

...Sched<[WriteFAddLd, ReadAfterLd]>; > > // Accept explicit immediate argument form instead of comparison code. > let isAsmParserOnly = 1, hasSideEffects = 0 in { > def rri_alt : PIi8<0xC2, MRMSrcReg, > (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc), > asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>; > def rmi_alt : PIi8<0xC2, MRMSrcMem, > (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc), > asm_alt, [], itins.rm, d>, > Sched<[WriteFAddL...

hi, some instructions mismatch between assembler & disassembler, like below. it seems this happens with all SSECC related instructions? thanks, Jun $ echo "cmpps xmm1, xmm2, 23" | ./Release+Asserts/bin/llvm-mc -assemble -triple=x86_64 --output-asm-variant=1 -x86-asm-syntax=intel -show-encoding .text cmpps xmm1, xmm2, 23 # encoding: [0x0f,0xc2,0xca,0x17] $

...hich reads assembly instructions and produces the equivalent binary. I have a problem. Although I set the bit range and immediate type for an instruction like add which accepts a register and an immediate value, I can simply overflow that value and llvm/tablegen doesn't care! for example for a i8imm imm value (bits<8> val) these two produce the same output: add r0 0 add r0 256 whose responsibility is to check the integer boundary in the assembly parser? Cheers, ES -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-d...

What does MIOperandInfo exactly mean while defining an Operand class? e.g. here class X86MemOperand<string printMethod> : Operand<iPTR> { let PrintMethod = printMethod; let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm); } -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20071204/23db1ace/attachment.html>

...TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m, 0xF6>; // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the // register class is constrained to GR8_NOREX. let isPseudo = 1 in def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src, i8imm:$mask), "", [], IIC_BIN_NONMEM>, Sched<[WriteALU]>; } // Defs = [EFLAGS] def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL, "{$src, %al|al, $src}">; def TEST16i16 : BinOpAI<0xA8, "test&qu...

...LVM to use SUB8ri in the most straightforward case that would work for me. Thanks, Joshua // SUB8ri definition let Constraints = "$src = $dst" in def SUB8ri : Instruction { let Namespace = "AVR"; dag OutOperandList = (outs GPR8:$dst); dag InOperandList = (ins GPR8:$src, i8imm:$src2); let AsmString = "SUB\t{$dst, $src2}"; let Pattern = [(set GPR8:$dst, (opnode GPR8:$src, imm:$src2))]; } Joshua Nedrud Master of Science, Biomedical Engineering

...= 0b1; let Inst{14-13} = 0b00; let Inst{12-8} = 0b01101; let Inst{7-0} = opcode; } and I have def pcoffset8 : Operand<i8>, ImmLeaf<i8, [{ return Immediate >= -128 && Immediate <= 127; }]> { let PrintMethod = "printPCRelImmOperand"; let MIOperandInfo = (ops i8imm); let ParserMatchClass = ImmediateAsmOperand<"Imm8">; let EncoderMethod = "getMemOpValue"; let DecoderMethod = "DecodeMemOperand"; } def pcoffset16 : Operand<i16>, ImmLeaf<i16, [{ return Immediate >= -32768 && Immediate <= 32767; }]&...

...; needs to be scalar>>), like in the following complete specification: // Inspired heavily from lib/Target/X86/X86InstrInfo.td class X86MemOperand<string printMethod> : Operand<iPTR> { let PrintMethod = printMethod; let MIOperandInfo = (ops i8imm, i32imm); let OperandType = "OPERAND_MEMORY"; } // Gather mem operands class X86VMemOperand<RegisterClass RC, string printMethod> : X86MemOperand<printMethod> { let MIOperandInfo = (ops i8imm, RC, i32imm);...

...hey are the same or not). In the following example, two 'regsw' are used to match the operands of mul. def regsw : Operand<v4i32>, ComplexPattern<v4i32, 2, "SelectRegsw", []> { let PrintMethod = "printSrcReg"; let MIOperandInfo = (ops VR128, i8imm); } def MUL_1 : FooInst<(outs VR128:$dst), (ins regsw:$src0, regsw:$src1), "mul $dst, $src0, $src1", [(set VR128:$dst, (mul regsw:$src0, regsw:$src1))]>; The code generate by TableGen is: SDNode *Select_ISD_MUL_v4i32(co...

Hello > and as the return value. Is this a missed optimization from LLVM or did i > miss something out? > Changing the register allocation order didnt work. What are the patterns for xor / mov ? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

...td file was augmented to specify the new op16 opcode for the new sub-target. Hence, no instructions are duplicated and this change has no effect on the custom lowering passes that can continue to hand-insert specific target instructions. def JUMP_cond : AJumpCC<0b110101, 0b110010, (outs), (ins i8imm:$cc, brtarget:$dst), "jump \t$cc, $dst", [(PBjumpcc simm8:$cc, bb:$dst)]>; Finally, I modified the build system to call "tablegen -gen-emitter" twice, first with "-emitter-instfld=Inst" to generate the encoder for KCP...

...calar>>), like in the following complete specification: > // Inspired heavily from lib/Target/X86/X86InstrInfo.td > class X86MemOperand<string printMethod> : Operand<iPTR> { > let PrintMethod = printMethod; > let MIOperandInfo = (ops i8imm, i32imm); > let OperandType = "OPERAND_MEMORY"; > } > // Gather mem operands > class X86VMemOperand<RegisterClass RC, string printMethod> > : X86MemOperand<printMethod> { > let MIOperandInfo = (ops i8imm...

Hello. Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have to say that the definition of the "multiclass avx512_gather" from lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it. I currently have some serious problems with TableGen - it gives an assertion failure:

...ctorSDNode>(N)); }], SHUFFLE_get_vperm2f128_imm>; I don't understand completely how the new system all works. Take a simple SHUFPS match: def SHUFPSrri : PSIi8<0xC6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3), "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR128:$dst, (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>; "shufp" is the magic bit here. It's definition looks like this...

Hello, while testing trivial functions in my backend i noticed a suboptimal way of assigning regs that had the following pattern, consider the following function: typedef unsigned short t; t foo(t a, t b) { t a4 = b^a^18; return a4; } Argument "a" is passed in R15:R14 and argument "b" is passed in R13:R12, the return value is stored in R15:R14. Producing the