search for: i32rc

...R1029, R1024, R1028 // incrementing the src pointer load R1030, R1029 add_pointer R1031, R1025,R1028 // calculating the dst address store R1030, R1031 mov R1031, 4 add R1032, R1026, R1031 //scalar addition ret Currently my ADD instruction is defined in the InstrInfo.td file as following: def I32RC : RegisterClass<"MyMachine", [i32], 32, [DefReg]>; def P32RC : RegisterClass<"MyMachine", [iPTR], 32, [DefReg]>; -> I get error from tablegen if I use iPTR def MyAdd : MyInst < myadd, nosubop, (outs I32RC:$dst), (ins I32RC:$src1, I32RC:$src2), “add $dst,...

...ter promote the store to a MOV (in a custom lowering step), and this code above is changing the register class, such that it won't coalesce. The debug output looks like this (%Xn are phys regs in F32RC regclass) -------------- BB#0: derived from LLVM BB %entry %vreg0<def> = MOV_I32_RI 1; I32RC:%vreg0 %X0<def> = COPY %vreg0; I32RC:%vreg0 %vreg1<def> = MOV_I32_RI 0; I32RC:%vreg1 %X1<def> = COPY %vreg1; I32RC:%vreg1 %X2<def> = COPY %vreg1; I32RC:%vreg1 RET # End machine code for function foo ********** SIMPLE REGISTER COALESCING ********** ********** Function: foo...

...rs which aren't naturally exposed in LLVM. Here's what I've done to add pointer support for an instruction called PADD that takes a pointers and an offset and returns the new pointer value: def DefReg : Register<"r">; def PtrReg : Register<"ptr">; def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>; def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>; def BEInst<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { /* assign arguments to class members */ } def BE_PADD : BE...

...> in LLVM. Here's what I've done to add pointer support for an > instruction > called PADD that takes a pointers and an offset and returns the new > pointer value: > > def DefReg : Register<"r">; > def PtrReg : Register<"ptr">; > def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>; > def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>; > def BEInst<bits<8> op, dag outs, dag ins, string asmstr, list<dag> > pattern> : Instruction { /* assign arguments to class members */ } &g...

...R1029, R1024, R1028 // incrementing the src pointer load R1030, R1029 add_pointer R1031, R1025,R1028 // calculating the dst address store R1030, R1031 mov R1031, 4 add R1032, R1026, R1031 //scalar addition ret Currently my ADD instruction is defined in the InstrInfo.td file as following: def I32RC : RegisterClass<"MyMachine", [i32], 32, [DefReg]>; def P32RC : RegisterClass<"MyMachine", [iPTR], 32, [DefReg]>; -> I get error from tablegen if I use iPTR def MyAdd : MyInst < myadd, nosubop, (outs I32RC:$dst), (ins I32RC:$src1, I32RC:$src2), “add $dst, $s...

...hat I've done to add pointer support for an >> instruction >> called PADD that takes a pointers and an offset and returns the new >> pointer value: >> >> def DefReg : Register<"r">; >> def PtrReg : Register<"ptr">; >> def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>; >> def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>; >> def BEInst<bits<8> op, dag outs, dag ins, string asmstr, list<dag> >> pattern> : Instruction { /* assign arguments to class m...

...nter support for an >>> instruction >>> called PADD that takes a pointers and an offset and returns the new >>> pointer value: >>> >>> def DefReg : Register<"r">; >>> def PtrReg : Register<"ptr">; >>> def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>; >>> def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>; >>> def BEInst<bits<8> op, dag outs, dag ins, string asmstr, list<dag> >>> pattern> : Instruction { /* assign arguments...

Hello, Everyone > TargetSelectoinDAG.td and then why the two versions are "identical" in > TableGen's mind. That's correct. The patterns are identical since the types of operands involved are the same. DAG pattern matching is done before regalloc, there are not regclasses actually at that point, thus both patterns tries to select the same thing... -- With best regards,