Displaying 7 results from an estimated 7 matches for "p32rc".
2009 Jul 04
2
[LLVMdev] Help on DAG pattern matching string
...ve done to add pointer support for an instruction
called PADD that takes a pointers and an offset and returns the new
pointer value:
def DefReg : Register<"r">;
def PtrReg : Register<"ptr">;
def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>;
def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>;
def BEInst<bits<8> op, dag outs, dag ins, string asmstr, list<dag>
pattern> : Instruction { /* assign arguments to class members */ }
def BE_PADD : BEInst<0F, (outs P32RC:$dst), (ins P32RC:$src1,
I32RC:$src2), "...
2009 Jul 04
0
[LLVMdev] Help on DAG pattern matching string
...> instruction
> called PADD that takes a pointers and an offset and returns the new
> pointer value:
>
> def DefReg : Register<"r">;
> def PtrReg : Register<"ptr">;
> def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>;
> def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>;
> def BEInst<bits<8> op, dag outs, dag ins, string asmstr, list<dag>
> pattern> : Instruction { /* assign arguments to class members */ }
> def BE_PADD : BEInst<0F, (outs P32RC:$dst), (ins P32RC:$src1,
> I3...
2009 Jul 07
1
[LLVMdev] LLVM code target dependent generator question
...inter R1031, R1025,R1028 // calculating the dst address
store R1030, R1031
mov R1031, 4
add R1032, R1026, R1031 //scalar addition
ret
Currently my ADD instruction is defined in the InstrInfo.td file as following:
def I32RC : RegisterClass<"MyMachine", [i32], 32, [DefReg]>;
def P32RC : RegisterClass<"MyMachine", [iPTR], 32, [DefReg]>; -> I get error from tablegen if I use iPTR
def MyAdd : MyInst
<
myadd,
nosubop,
(outs I32RC:$dst),
(ins I32RC:$src1, I32RC:$src2),
“add $dst, $src1, $src2",
[(set rc:$dst, (add I32RC:$src1, I32RC:$src2))]
def MyP...
2009 Jul 06
2
[LLVMdev] Help on DAG pattern matching string
...alled PADD that takes a pointers and an offset and returns the new
>> pointer value:
>>
>> def DefReg : Register<"r">;
>> def PtrReg : Register<"ptr">;
>> def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>;
>> def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>;
>> def BEInst<bits<8> op, dag outs, dag ins, string asmstr, list<dag>
>> pattern> : Instruction { /* assign arguments to class members */ }
>> def BE_PADD : BEInst<0F, (outs P32RC:$dst), (ins P32RC:...
2009 Jul 07
0
[LLVMdev] LLVM code target dependent generator question
...inter R1031, R1025,R1028 // calculating the dst address
store R1030, R1031
mov R1031, 4
add R1032, R1026, R1031 //scalar addition
ret
Currently my ADD instruction is defined in the InstrInfo.td file as following:
def I32RC : RegisterClass<"MyMachine", [i32], 32, [DefReg]>;
def P32RC : RegisterClass<"MyMachine", [iPTR], 32, [DefReg]>; -> I get error from tablegen if I use iPTR
def MyAdd : MyInst
<
myadd,
nosubop,
(outs I32RC:$dst),
(ins I32RC:$src1, I32RC:$src2),
“add $dst, $src1, $src2",
[(set rc:$dst, (add I32RC:$src1, I32RC:$src2))]
def MyPoi...
2009 Jul 06
0
[LLVMdev] Help on DAG pattern matching string
...pointers and an offset and returns the new
>>> pointer value:
>>>
>>> def DefReg : Register<"r">;
>>> def PtrReg : Register<"ptr">;
>>> def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>;
>>> def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>;
>>> def BEInst<bits<8> op, dag outs, dag ins, string asmstr, list<dag>
>>> pattern> : Instruction { /* assign arguments to class members */ }
>>> def BE_PADD : BEInst<0F, (outs P32RC:$dst), (...
2009 Jul 06
1
[LLVMdev] Help on DAG pattern matching string
Hello, Everyone
> TargetSelectoinDAG.td and then why the two versions are "identical" in
> TableGen's mind.
That's correct. The patterns are identical since the types of operands
involved are the same. DAG pattern matching is done before regalloc,
there are not regclasses actually at that point, thus both patterns
tries to select the same thing...
--
With best regards,