search for: i32i8imm

Displaying 11 results from an estimated 11 matches for "i32i8imm".

2009 Jun 17
3
[LLVMdev] Regular Expressions
...} class X86_v8f32 : X86ValueType { let VT = v8f32; let RegClass = VR256; let suffix = "ps"; } Ok, you get the picture. Now let's look at how we would write instruction patterns: defm BLENDPS : sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0C, i32i8imm, "blend", "blend", "f32">; defm BLENDPD : sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0D, i32i8imm, "blend", "blend", "f64">; We have to send types as strings because we need to be able to munge them...
2009 Jun 17
0
[LLVMdev] Regular Expressions
On Tuesday 16 June 2009 19:35, David Greene wrote: > So which is more intuitive and less error-prone? > > defm BLENDPS : sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0C, > i32i8imm, "blend", "blend", "f32", 4>; > > or > > defm BLENDPS : sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0C, > i32i8imm, "blendps", "blendps">; Here's another option: defm BLENDPS : sse41_avx_fp...
2013 Jul 11
1
[LLVMdev] [PATCH] x86: disambiguate unqualified btr, bts
On Wednesday 10 July 2013 22:18:23 Jevin Sweval wrote: > http://www.cs.fsu.edu/~baker/devices/lxr/http/source/linux/arch/x86/include/ > asm/bitops.h#L68 > > Here is one example that I found. Are the inline assembly arguments > ambiguous in size? It would help us for sure to build the kernel and others. -- JS
2009 Jun 15
0
[LLVMdev] Regular Expressions
On Jun 15, 2009, at 11:33 AM, David Greene wrote: > To reduce redundancy, developers must be able to write generic > patterns > like this: > > [(set DSTREGCLASS:$dst, // rr, rrr > (xor (INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src1))), > (INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src2)))))], > > The substitution then fills in the appropriate types,
2009 Jun 15
2
[LLVMdev] Regular Expressions
Chris Lattner wrote: > However, I don't see any reason to base this off of strings. Instead > of passing down "f32" as a string, why not do something like this > pseudo code: > > class X86ValueType { > RegisterClass RegClass; > ... > } > > def X86_f32 : X86ValueType { > let RegClass = FR32; > ... }; > def X86_i32 :
2009 Jun 17
2
[LLVMdev] Regular Expressions
...n Jun 16, 2009, at 5:49 PM, David Greene wrote: > On Tuesday 16 June 2009 19:35, David Greene wrote: > >> So which is more intuitive and less error-prone? >> >> defm BLENDPS : >> sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0C, >> i32i8imm, "blend", "blend", "f32", 4>; >> >> or >> >> defm BLENDPS : >> sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0C, >> i32i8imm, "blendps", "blendps">; > > Here's anothe...
2009 Dec 03
2
[LLVMdev] Duplicate Label in Generates ISel
I've got the following problem in the X86 selector generated by TableGen: llvm/lib/Target/X86/X86GenDAGISel.inc:91821: error: duplicate case value llvm/lib/Target/X86/X86GenDAGISel.inc:91442: error: previously used here This seems to happen because of a pattern I added for VEXTRACTF128 which uses extract_subreg: [(set DSTREGCLASS:$dst, (DSTTYPE (extract_subreg
2009 Dec 03
0
[LLVMdev] Duplicate Label in Generates ISel
...def), > (SRCTYPE SRCREGCLASS:$src1), > VEXTRACTF128_shuffle_mask:$src2), > x86_subreg_128bit)))], > > def x86_subreg_128bit : PatLeaf<(i32 1)>; Whoops, I forgot to fill in types: (outs VR128:$dst), (ins VR129:$src1, i32i8imm:$src2) [(set DSTREGCLASS:$dst, (v4f32 (extract_subreg (vector_shuffle (v8f32 undef), (v8f32 SRCREGCLASS:$src1), VEXTRACTF128_shuffle_mask:$src2), x86_subreg_128bit)))],...
2009 Dec 03
1
[LLVMdev] Duplicate Label in Generates ISel
On Thursday 03 December 2009 13:43, David Greene wrote: > Whoops, I forgot to fill in types: > > (outs VR128:$dst), (ins VR129:$src1, i32i8imm:$src2) > > [(set DSTREGCLASS:$dst, > (v4f32 (extract_subreg > (vector_shuffle > (v8f32 undef), > (v8f32 SRCREGCLASS:$src1), > VEXTRACTF128_shuffle_mask:$src2), > x86_subr...
2013 Jul 10
3
[LLVMdev] [PATCH] x86: disambiguate unqualified btr, bts
...a/lib/Target/X86/X86InstrInfo.td > +++ b/lib/Target/X86/X86InstrInfo.td > @@ -1971,6 +1971,10 @@ def : InstAlias<"aam", (AAM8i8 10)>; > // Disambiguate the mem/imm form of bt-without-a-suffix as btl. > def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>; > > +// Disambiguate btr and bts, just like GNU as. > +def : InstAlias<"btr $imm, $mem", (BT16mi8 i16mem:$mem, i16i8imm:$imm)>; > +def : InstAlias<"bts $imm, $mem", (BT16mi8 i16mem:$mem, i16i8imm:$imm)>; > + > // clr aliases. > def :...
2013 Jul 10
0
[LLVMdev] [PATCH] x86: disambiguate unqualified btr, bts
...86/X86InstrInfo.td >> +++ b/lib/Target/X86/X86InstrInfo.td >> @@ -1971,6 +1971,10 @@ def : InstAlias<"aam", (AAM8i8 10)>; >> // Disambiguate the mem/imm form of bt-without-a-suffix as btl. >> def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>; >> >> +// Disambiguate btr and bts, just like GNU as. >> +def : InstAlias<"btr $imm, $mem", (BT16mi8 i16mem:$mem, i16i8imm:$imm)>; >> +def : InstAlias<"bts $imm, $mem", (BT16mi8 i16mem:$mem, i16i8imm:$imm)>; >> + >> //...