Displaying 7 results from an estimated 7 matches for "i1_".
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i16
2009 Mar 16
2
[LLVMdev] Overlapping register classes
...subregs
> are emitted with a copy (MOV32to32_) to put the value in a virtual
> register of the needed class. This copy may then optimized away
> by subsequent passes.
I missed this before (thanks, Eli). I tried adding the explicit move
patterns, and at least it compiles correctly now:
i1_ls:
R0.H = HI(i1_l); R0.L = LO(i1_l);
P0 = R0;
R0.H = HI(i1_s); R0.L = LO(i1_s);
R1 = B[P0] (Z);
R2 = 1 (X);
P0 = R0;
R0 = R1 & R2;
B[P0] = R0;
RTS;
The moves (P0 = R0) did not get optimized away by the register
allocator. RALinScan::attemptTrivialCoalescing almost succeeded; it got
a...
2009 Mar 15
5
[LLVMdev] Overlapping register classes
...[(set GR:$dst, imm:$src)]>;
I think I am stretching the code generator beyond its capability by
doing this. As far as I can tell, instruction selection is done purely
based on value types. Register classes are not considered.
I get in trouble when I try to compile this function:
@i1_l = external global i1
@i1_s = external global i1
define void @i1_ls() nounwind {
%tmp = load i1* @i1_l
store i1 %tmp, i1* @i1_s
ret void
}
Instruction selection works correctly, but the scheduling step fails
with "Register class of operand and regclass of use don't agree!" in
Sc...
2009 Mar 17
0
[LLVMdev] Overlapping register classes
...a copy (MOV32to32_) to put the value in a virtual
>> register of the needed class. This copy may then optimized away
>> by subsequent passes.
>
> I missed this before (thanks, Eli). I tried adding the explicit move
> patterns, and at least it compiles correctly now:
>
> i1_ls:
> R0.H = HI(i1_l); R0.L = LO(i1_l);
> P0 = R0;
> R0.H = HI(i1_s); R0.L = LO(i1_s);
> R1 = B[P0] (Z);
> R2 = 1 (X);
> P0 = R0;
> R0 = R1 & R2;
> B[P0] = R0;
> RTS;
>
> The moves (P0 = R0) did not get optimized away by the register
> allocator. RAL...
2009 Mar 16
0
[LLVMdev] Overlapping register classes
...]>;
>
> I think I am stretching the code generator beyond its capability by
> doing this. As far as I can tell, instruction selection is done purely
> based on value types. Register classes are not considered.
>
> I get in trouble when I try to compile this function:
>
> @i1_l = external global i1
> @i1_s = external global i1
>
> define void @i1_ls() nounwind {
> %tmp = load i1* @i1_l
> store i1 %tmp, i1* @i1_s
> ret void
> }
>
> Instruction selection works correctly, but the scheduling step fails
> with "Register class of operand...
1999 May 04
1
rnorm
Brian
I've been playing a bit with the Wichmann-Hill RNG. I would prefer to have
normally distributed random numbers and I think I have things generally worked
out to use Wichmann-Hill and then Box-Muller. In the process, I was looking at
R's rnorm.c, but could not figure out what transformation is used in R to
convert uniform rv's to normal rv's. Do you know? It looks like there
1999 Feb 24
2
Compiling R on Sunos
I'm looking for some help in getting R to compile on Sunos. We run a
collection of Sunos and Solaris machines in the department here. I got
to compile on Solaris 2.5.1 using gcc 2.7.2.2. On my Sunos 4.1.3 (and
I've tried it on Sunos 4.1.4 as well) machines, it crashes during the
compile. I'm using gcc 2.8.1 on there. It gets to this point:
gcc -g -O2 -I../include
2001 Nov 14
0
OPEN ssh pkg
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