search for: i193

Displaying 7 results from an estimated 7 matches for "i193".

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2015 Feb 02
3
[LLVMdev] LLVM IR i128
...gs/show_bug.cgi?id=20011 (crash with <2 x i2>) http://llvm.org/bugs/show_bug.cgi?id=20012 (error when storing <2 x i4>) http://llvm.org/bugs/show_bug.cgi?id=19797 (assert failure on multiplication of i192) http://llvm.org/bugs/show_bug.cgi?id=20921 (assert failure on stores and loads of i193) http://llvm.org/bugs/show_bug.cgi?id=21184 (miscompilation of wider-than-legal types) I would *really* wish that the documentation made sure to mention, that wider-than-legal types are not expected to work. - Jaak
2011 Jul 17
0
[LLVMdev] Trying to optimize out store/load pair
...l nsw i32 %sub6.i184, 459 %add18.i187 = add i32 %tmp.i185, -4640 %add19.i188 = add i32 %mul17.i186, %add18.i187 %shr.i189 = ashr i32 %add19.i188, 8 %mul26.i190 = mul nsw i32 %sub.i183, -55 %mul30.i191 = mul nsw i32 %sub6.i184, -136 %add31.i192 = add i32 %add18.i187, %mul26.i190 %add32.i193 = add i32 %add31.i192, %mul30.i191 %shr33.i194 = ashr i32 %add32.i193, 8 %mul40.i195 = mul nsw i32 %sub.i183, 541 %add46.i196 = add i32 %add18.i187, %mul40.i195 %shr47.i197 = ashr i32 %add46.i196, 8 store i32 %tmp, i32* %x139, align 4, !tbaa !2 store i32 %tmp26, i32* %y141, align 4, !tb...
2011 Jul 17
0
[LLVMdev] Trying to optimize out store/load pair
...86 = mul nsw i32 %sub6.i184, 459 %add18.i187 = add i32 %tmp.i185, -4640 %add19.i188 = add i32 %mul17.i186, %add18.i187 %shr.i189 = ashr i32 %add19.i188, 8 %mul26.i190 = mul nsw i32 %sub.i183, -55 %mul30.i191 = mul nsw i32 %sub6.i184, -136 %add31.i192 = add i32 %add18.i187, %mul26.i190 %add32.i193 = add i32 %add31.i192, %mul30.i191 %shr33.i194 = ashr i32 %add32.i193, 8 %mul40.i195 = mul nsw i32 %sub.i183, 541 %add46.i196 = add i32 %add18.i187, %mul40.i195 %shr47.i197 = ashr i32 %add46.i196, 8 store i32 %tmp, i32* %x139, align 4, !tbaa !2 /// these stores should be...
2010 Sep 29
0
[LLVMdev] spilling & xmm register usage
...p31.i187.i, 0x3FFC80EF00000000 > %tmp33.i189.i = fmul float %tmp7.i163.i, %tmp32.i188.i > %tmp34.i190.i = fadd float %tmp33.i189.i, 0xBFD6D1F0E0000000 > %tmp35.i191.i = fmul float %tmp7.i163.i, %tmp34.i190.i > %tmp36.i192.i = fadd float %tmp35.i191.i, 0x3FD470BF40000000 > %tmp37.i193.i = fmul float %tmp19.i175.i, %tmp36.i192.i > %tmp38.i194.i = fsub float 1.000000e+00, %tmp37.i193.i > %cmp.i197.i = fcmp olt float %tmp11.i29.i, 0.000000e+00 > br i1 %cmp.i197.i, label %cond.then.i201.i, label %entry.header.loop.end > > cond.then.i201.i:...
2015 Feb 02
3
[LLVMdev] LLVM IR i128
Hi everyone! Here, I have a question and am curious about i128. I want to know how the LLVM handle i128, because many compiler backend doesn't support i128 directly. So I am very curious and want to how the llvm handle this situation? Besides i128, such as i256, i512, even i24? Thanks. Best Regards Wu Zhao -------------- next part -------------- An HTML attachment was scrubbed...
2010 Sep 29
3
[LLVMdev] spilling & xmm register usage
Hello everybody, I have stumbled upon a test case (the attached module is a slightly reduced version) that shows extremely reduced performance on linux compared to windows when executed using LLVM's JIT. We narrowed the problem down to the actual code being generated, the source IR on both systems is the same. Try compiling the attached module: llc -O3 -filetype=asm -o BAD.s BAD.ll Under
2013 Feb 14
1
[LLVMdev] LiveIntervals analysis problem
...label %eshup1.exit244.i, label %for.body.i225.i eshup1.exit244.i: ; preds = %if.end.i243.i call fastcc void @eaddm(i16* %arraydecay15.i, i16* %arraydecay94.i) nounwind br label %for.body.i175.i for.body.i175.i: ; preds = %if.end.i193.i, %eshup1.exit244.i %i.025.i171.i = phi i32 [ 2, %eshup1.exit244.i ], [ %inc.i191.i, %if.end.i193.i ] %bits.024.i172.i = phi i16 [ 0, %eshup1.exit244.i ], [ %conv15.i189.i, %if.end.i193.i ] %x.addr.023.i173.i = phi i16* [ %scevgep.i.i, %eshup1.exit244.i ], [ %incdec.ptr.i190.i, %if.end.i193....