Displaying 20 results from an estimated 1550 matches for "i16s".
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i16
2013 Feb 14
1
[LLVMdev] LiveIntervals analysis problem
Hello everyone,
please I need your help.
To reproduce my problem I created simple pass for backends (TestPass.cpp
in attached files). That pass I call from Mips backend in this way
(MipsTargetMachine.cpp):
bool MipsPassConfig::addPreRegAlloc() {
addPass(createTestPass());
return false;
}
The problem becomes, when I am trying compile file ldtoa.ll (in attached
files). Compiling
2012 Nov 26
2
[LLVMdev] LSR pass
Hi,
I would like some help regarding the LSR pass. It seems that it likes to duplicate address calculations as in the case above, which is highly undesirable on my target.
I wonder if there is any way to tell LSR to not duplicate the code in cases like this? Or could I perhaps run CSE after LSR again?
What is the logic behind this transformation? It seems that a LSR pass should not insert a
2016 Mar 30
2
Instruction selection pattern for intrinsic returning llvm_any_ty
Hi,
On 03/30/2016 11:15 AM, Matt Arsenault wrote:
>
>> On Mar 30, 2016, at 09:33, Mikael Holmén via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>>
>> Hi,
>>
>> On my out-of-tree target I have an intrinsic
>>
>> def int_phx_divm_u16 : Intrinsic<[llvm_any_ty],
>> [llvm_i16_ty, llvm_i16_ty],
>>
2016 Mar 30
2
Instruction selection pattern for intrinsic returning llvm_any_ty
Hi,
On my out-of-tree target I have an intrinsic
def int_phx_divm_u16 : Intrinsic<[llvm_any_ty],
[llvm_i16_ty, llvm_i16_ty],
[IntrNoMem]>;
that I want to translate to the following instruction during instruction
selection:
def divm16_pseudo : MyPseudoInst<
(outs aNh_0_7:$dst, aNh_0_7:$dst2),
(ins
2015 Jan 23
2
[LLVMdev] question about enabling cfl-aa and collecting a57 numbers
Without the patch is also returns the wrong answer for all of these, it
just doesn't cause LICM to promote because it returns PartialAlias (which
is still wrong).
We return may-alias instead, and now suddenly it's happy to promote them.
The broken noalias results exist both before and after my patch:
===== Alias Analysis Evaluator Report =====
521 Total Alias Queries Performed
2015 Jan 24
2
[LLVMdev] question about enabling cfl-aa and collecting a57 numbers
No, i mean the actual store instruction looks like "store i16 %conv22, i16*
getelementptr inbounds ([16 x i16]* @pA, i64 0, i64 12), align 2, !tbaa !1"
Not that the pointer operand comes from a GEP, but it is a constantexpr,
whose opcode is GEP.
It sucks that there is such a complex thing to be handled as a store
operand directly , but such is life ...
CFL-AA *should* treat this
2008 Sep 08
2
[LLVMdev] Overzealous PromoteCastOfAllocation
Hi all,
I'm currently running into some problems with instcombine changing the type of
alloca instructions. In particular, the PromoteCastOfAllocation looks at any
allocation instruction that is used by a bitast.
It does a few checks, but basically tries to change the type of the alloca
instruction to the type pointed to by the bitcasted type. The current
heuristic for determining if this is
2011 May 03
3
[LLVMdev] GVN Infinite loop
Hi,
GVN seems to be running in an infinite loop on my example. I have attached
the output of one iteration. I cant seem to reduce the testcase either.
Any pointers to how to reduce the test case.
THanks,
Arushi
GVN iteration: 8
GVN WIDENED LOAD: %0 = load i8* getelementptr inbounds
(%struct.CHESS_POSITION* @search, i64 0, i32 23), align 2, !dbg !875
TO: %1 = load i16* bitcast (i8*
2016 Mar 30
0
Instruction selection pattern for intrinsic returning llvm_any_ty
> On Mar 30, 2016, at 09:33, Mikael Holmén via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> Hi,
>
> On my out-of-tree target I have an intrinsic
>
> def int_phx_divm_u16 : Intrinsic<[llvm_any_ty],
> [llvm_i16_ty, llvm_i16_ty],
> [IntrNoMem]>;
>
> that I want to translate to the
2013 Jan 18
2
[LLVMdev] Weird volatile propagation ?
Hi All,
Using clang+llvm at head, I noticed a weird behaviour with the following
reduced testcase :
$ cat test.c
#include <stdint.h>
struct R {
uint16_t a;
uint16_t b;
};
volatile struct R * const addr = (volatile struct R *) 416;
void test(uint16_t a)
{
struct R r = { a, 1 };
*addr = r;
}
$ clang -O2 -o - -emit-llvm -S -c test.c
; ModuleID = 'test.c'
target
2014 Sep 30
2
[LLVMdev] Behaviour of NVPTX intrinsic
I have written test.ll as below and ran 'opt' on it as
" opt -std-compile-opts test.ll -S -o -" . But the output shows that there
is code motion around the barrier intrinsics.
test.ll
-------
; ModuleID = 'test.bc'
define void @test(i16* %I_0, i16* %I_1, i16* %I_2, i16* %I_3, i16* %O_0) {
entry:
%T_0 = load volatile i16* %I_0
%T_1 = load volatile i16* %I_1
%T_2 =
2016 Mar 30
2
Instruction selection pattern for intrinsic returning llvm_any_ty
Hi,
On 03/30/2016 11:38 AM, Matt Arsenault wrote:
>
>> On Mar 30, 2016, at 11:35, Mikael Holmén <mikael.holmen at ericsson.com
>> <mailto:mikael.holmen at ericsson.com>> wrote:
>>
>> i16 (divm16_pseudo …)
>>
>> stuff?
>>
>> I've tried
>> (i16, i16 (divm16_pseudo i16:$src1, i16:$src2)
>> and
>> ((i16, i16)
2015 Jan 23
2
[LLVMdev] question about enabling cfl-aa and collecting a57 numbers
Works for me
On Thu, Jan 22, 2015 at 8:27 PM, Daniel Berlin <dberlin at dberlin.org> wrote:
> We should use graph edges, so we can do something better at set build time
> :)
>
>
> On Thu Jan 22 2015 at 5:20:46 PM George Burgess IV <
> george.burgess.iv at gmail.com> wrote:
>
>> > Should we be added an edge from the inttoptr to all other pointer
>>
2015 Aug 07
2
load instruction erroneously removed by GVN
Hi,
I'm having a problem with GVN removing a load instruction that I think
is needed.
Dump before GVN:
*** IR Dump Before Global Value Numbering ***
; Function Attrs: minsize optsize
define i16 @TEST__MAIN(i16 %argc.13.par, i16** %argv.14.par) #0 {
%buf.17 = alloca [10 x i16], align 1
%_tmp30 = getelementptr inbounds [10 x i16], [10 x i16]* %buf.17, i16
0, i16 0, !dbg !22
call
2015 Jan 26
2
[LLVMdev] question about enabling cfl-aa and collecting a57 numbers
> Fixing that still gives a wrong result, i haven't started to track down
what *else* is going on here.
Running with the attached diff + a modified buildGraphFrom to handle the
constexpr GEPs, we seem to flag everything in test2.ll (conservatively)
correctly.
Is `store` the only place we can expect to see these constexpr analogs, or
is just about anywhere fair game?
George
On Fri, Jan
2018 May 04
0
How to constraint instructions reordering from patterns?
Here is a last example to illustrate my concern.
The problem is about the lowering of node t13.
Initial selection DAG: BB#0 '_start:entry'
SelectionDAG has 44 nodes:
t11: i16 = Constant<0>
t0: ch = EntryToken
t3: ch = llvm.clp.set.rspa t0, TargetConstant:i16<392>, Constant:i32<64>
t5: ch = llvm.clp.set.rspb t3,
2011 May 04
0
[LLVMdev] GVN Infinite loop
On May 3, 2011, at 3:25 PM, Arushi Aggarwal wrote:
> Hi,
>
> GVN seems to be running in an infinite loop on my example. I have attached the output of one iteration. I cant seem to reduce the testcase either.
>
> Any pointers to how to reduce the test case.
Bugzilla can reduce testcases that cause infinite loops (it has a -timeout flag), I'd try it. Even if this doesn't
2016 Jul 20
2
load instruction erroneously removed by GVN v2
Hello to whom this may concern,
Versioned this as I saw identical title before. I'm compiling a clang
project where I'm seeing GVN mess up and replace a load with a wrong def
value. I am using LLVM-3.5, but the problem has been observed upto 3.8.
To illustrate the problem,
define i32 @main
scalar.ph:
<initialize [80 x i16] %dest>
...
preheader:
%index=0
br test, loop1, bb2
2019 Jun 05
2
Strange behaviour of post-legalising optimisations(?)
I come across a situation that I am having a hard time to understand.
When I compile the following code :
char *tst( char *dest, const char *src, unsigned int len )
{
for (int i=0 ; i<len ; i++) {
dest[i] = src[i];
}
return dest;
}
Clang generates this for the ‘for’ body:
for.body: ; preds = %for.cond
%arrayidx = getelementptr inbounds i8,
2018 May 04
2
How to constraint instructions reordering from patterns?
The DAG dumping will try to print some of the nodes "inline" (i.e. where
they are used) to make the output more readable, so the dump of the DAG
may not strictly reflect the node ordering.
-Krzysztof
On 5/4/2018 8:18 AM, Dominique Torette via llvm-dev wrote:
> Here is a last example to illustrate my concern.
>
> The problem is about the lowering of node t13.
>
>