search for: i128mem

Displaying 6 results from an estimated 6 matches for "i128mem".

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2007 Aug 01
2
[LLVMdev] Adding custom operation intrinsic for ASIP architectures.
.... > def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">, > Intrinsic<[llvm_void_ty, llvm_ptr_ty, > llvm_v4f32_ty], [IntrWriteMem]>; > } > > and lib/Target/X86/X86InstrSSE.td contains: > > def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, > VR128:$src), > "movntps {$src, $dst|$dst, $src}", > [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>; > > There is corresponding code in llvm-gcc to tell GCC how to handle this > builtin. Is this what you're looking for? > Yes this is more or less, wha...
2007 Aug 02
0
[LLVMdev] Adding custom operation intrinsic for ASIP architectures.
On Wed, 1 Aug 2007, [UTF-8] Mikael Lepist? wrote: >> def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, >> VR128:$src), >> "movntps {$src, $dst|$dst, $src}", >> [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>; >> >> There is corresponding code in llvm-gcc to tell GCC how to handle this >> builtin. Is this what you're looking for? >> &...
2007 Aug 01
0
[LLVMdev] Adding custom operation intrinsic for ASIP architectures.
...ef int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">, Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>; } and lib/Target/X86/X86InstrSSE.td contains: def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), "movntps {$src, $dst|$dst, $src}", [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>; There is corresponding code in llvm-gcc to tell GCC how to handle this builtin. Is this what you're looking for? -Chris -- http://n...
2007 Jul 31
3
[LLVMdev] Adding custom operation intrinsic for ASIP architectures.
Hi, I was talking with aKor in #llvm how we could implement custom operation support for our ASIP architecture. We came into solution that the best way would be to write new custom operation intrinsic and optimization pass for raising certain type of function calls to those intrinsics (similar to raising mallocs). Basically our custom operation are like calls, with operand name and multiple
2017 Dec 11
2
New x86 instruction with opcode 0x0F 0x7A
Hi all, I'm trying to simulate an extended x86 architecture on gem5 with several new instructions. My hardware setup is done and now I'd like llvm to accept the existence of the new instruction passed in inline assembly and output the correct opcode and registers. I chose the two-byte opcode 0x0F 0x7A and I would like the instruction to have the same operands and return values as CVTPS2PI
2007 Aug 02
1
[LLVMdev] Adding custom operation intrinsic for ASIP architectures.
Chris Lattner wrote: > On Wed, 1 Aug 2007, [UTF-8] Mikael Lepist? wrote: > >>> def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, >>> VR128:$src), >>> "movntps {$src, $dst|$dst, $src}", >>> [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>; >>> >>> There is corresponding code in llvm-gcc to tell GCC how to handle this >>> builtin. Is this what you're...