search for: hwsync

> Longer term, I hope to improve the fence elimination of the ARM backend with > a kind of PRE algorithm. Both of these improvements to the ARM backend > should be fairly straightforward to port to the POWER architecture later, > and I hope to also do that. > > Any reason these couldn't be done at the IR level? I definitely agree here. At the time, it was a plausible idea

...it, then the transformation itself is wrong). Do you have an example execution in mind that shows it? > Since > these fences are not chosen based on the LLVM fences semantics, but on the > hardware memory model, I was thinking of inserting target-specific > intrinsics (dmb/isb on ARM, hwsync/lwsync/isync on Power), to make it > clearer that these passes are target-specific and unsound outside of their > target. If they *are* unsound, that should be changed immediately (and I'll almost certainly make time to do so, hence my questions here). It's completely unacceptable to...