Displaying 14 results from an estimated 14 matches for "hwencod".
Did you mean:
lencod
2017 Feb 10
2
generated HWEncoding based register decoders
Is there any reason why we can't generate HWEncoding based decoders for registers for mc disassemblers?
This is a concept patch to explore wether it'd work, and for my target, it does the right thing. I have one case where I have to shift a field over 2 bits, but I handle that in the glue. If I had a HWEncoding encoding on a per register cl...
2014 Jul 31
3
[LLVMdev] initialize register attributes in instruction definition
...define an instruction?
like
if a register is defined like this:
" class SC_Register<bits<8> register_num,
REG_FLAG SC_X,
REG_FLAG SC_Y,
REG_FLAG SC_Z,
REG_FLAG SC_W,
string asmstr> : Register<asmstr>
{
let HWEncoding{7-0} = register_num; // register_num
let HWEncoding{8} = SC_X;
let HWEncoding{9} = SC_Y;
…..
}”
can I set up the input/ouput register flags like this? or some other way in codegen to make the register flags are set up based on the instructions?
let Constraints = “$dst...
2014 Aug 01
2
[LLVMdev] initialize register attributes in instruction definition
..." class SC_Register<bits<8> register_num,
>> REG_FLAG SC_X,
>> REG_FLAG SC_Y,
>> REG_FLAG SC_Z,
>> REG_FLAG SC_W,
>> string asmstr> : Register<asmstr>
>> {
>>
>> let HWEncoding{7-0} = register_num; // register_num
>> let HWEncoding{8} = SC_X;
>> let HWEncoding{9} = SC_Y;
>> …..
>> }”
>>
>> can I set up the input/ouput register flags like this? or some other way in codegen to make the register flags are set...
2016 Aug 23
2
How to describe the RegisterInfo?
...espace = "IntelGPU" in {
foreach Index = 0-15 in {
def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
}
}
class IntelGPUReg<string n, bits<13> regIdx> : Register<n> {
bits<2> HStride;
bits<1> regFile;
let Namespace = "IntelGPU";
let HWEncoding{12-0} = regIdx;
let HWEncoding{15} = regFile;
}
// here I define the whole 4096 byte registers
foreach Index = 0-4095 in {
def Rb#Index : IntelGPUReg <"Rb"#Index, Index> {
let regFile = 0;
}
}
// b-->byte w-->word d-->dword q-->qword
// the set of unifo...
2017 Feb 10
2
generated HWEncoding based register decoders
On Feb 10, 2017, at 6:58 AM, Hal Finkel <hfinkel at anl.gov> wrote:
> I suspect that, for many targets, this is possible. It is just that no one has done the work to make this happen.
Ah, ok, just surprising to me then, as I find it more palatable to write the generator than to produce the list.
> So that we're on the same page, I believe you're talking about getting rid of
2013 Jun 05
1
[LLVMdev] TableGen lookup table recipe?
...as a list in tablegen, to map one
value to another? Here's the template I was working on:
=========================================
class LookupTable {
list<int> mapping = [0, 8, 16, 24, 32];
}
def LUT : LookupTable;
class MyRegister<name, index> : Register<name> {
let HWEncoding = LUT.mapping[index];
int otherVal = index; // required as well, ie. 'unmapped'
}
foreach reg 0-32 in {
def R#reg : MyRegister<!subst("X", reg, "rX"), reg>;
}
==========================================
TableGen complains that index is not an integer or...
2015 Sep 17
2
Register Number
Dear all,
in my TestRegisterInfo.td file, I defined a register like this:
class TestReg<bits<6> enc, string name> : Register<name> {
let HWEncoding{5-0} = enc;
let Namespace = "TEST";
}
def D0 : TestReg<0x01, "d0">, DwarfRegNum<[1]>;
but when I compile, the result I have in TestGenAsmMatcher.inc is this:
case 'd': // 7 strings to match.
switch (Name[1]) {
case '0': // 1 st...
2015 Sep 15
2
Parsing Operands at TableGen Level
Hi all,
is it possible in TableGen to set value to instruction bits based on the
operands?
In other words, parsing the instruction at the TableGen level.
for instance:
"add $Rd, $Rn, $imm"
I want to have something like this:
*Inst{8} = ($Rn == Test::A0) 1 : 0;*
Is there any way to do that in TableGen? If not is there any example in the
provided example codes?
Cheers,
ES
2017 Sep 19
0
[iovisor-dev] [PATCH RFC 3/4] New 32-bit register set
...he BPF register file
> //===----------------------------------------------------------------------===//
>
> +let Namespace = "BPF" in {
> + def sub_32 : SubRegIndex<32>;
> +}
> +
> +class Wi<bits<16> Enc, string n> : Register<n> {
> + let HWEncoding = Enc;
> + let Namespace = "BPF";
> +}
> +
> // Registers are identified with 4-bit ID numbers.
> // Ri - 64-bit integer registers
> -class Ri<bits<16> Enc, string n> : Register<n> {
> - let Namespace = "BPF";
> +class Ri<bits&...
2017 Jul 20
2
error:Ran out of lanemask bits to represent subregisterr
Hello Krzysztof,
The R_CASS definition is as follows:
class R_CASS<string n, bits<16> Enc, list<Register> subregs = []> :
Register<n> {
let Namespace = "X86";
let HWEncoding = Enc;
let SubRegs = subregs;
}
On Thu, Jul 20, 2017 at 4:14 AM, Krzysztof Parzyszek <
kparzysz at codeaurora.org> wrote:
> I tried reproducing the problem, but the file doesn't have everything I
> need (the class R_CLASS is not defined for example).
>
> Craig's g...
2019 Mar 25
2
Overlapping register groups in old 8-bit MC6809 processor.
...at describe the MC6809 register file
//===----------------------------------------------------------------------===//
class MC6809Reg<bits<4> num, string n, list<string> alt = []>
: Register<n> {
field bits<4> Num = num;
let Namespace = "MC6809";
let HWEncoding{3-0} = num;
let AltNames = alt;
}
class MC6809RegWithSubregs<bits<4> num, string n, list<Register> subregs, list<string> alt = []>
: RegisterWithSubRegs<n, subregs> {
field bits<4> Num = num;
let Namespace = "MC6809";
let HWEncoding{3-0} =...
2015 Sep 17
2
Register Number
...the encoding is 110, which I
> think is the bit 0 to 2 of what is the returned value in the
> TestGenAsmMatcher.inc.
> I mean, at the end, Inst{5-3} is getting a value which is not 001.
> What am I doing wrong?
>
I'm assuming that your TestReg definition assigns the 0x01 to the
HWEncoding field.
In an instruction definition, the way that tablegen assigns values from
the parameters is that it goes over all undefined fields in the
instruction class and assigns the values of the first argument to the
first undefined field, the value of the second argument to the second
undefine...
2016 Aug 23
2
How to describe the RegisterInfo?
Hi Escha,
Great to have your comment! Do you have any specific reason for not doing
like this?
I am not sure whether I understand your point correctly. For "just model
one thread",
do you mean "only considering ONE of the 8/16 working lanes that running in
lock-step way"??
For my case, may be something like I only need to define r0~r127 as
register for i32 register (each r#
2015 Sep 17
2
Register Number
On 9/17/2015 7:04 AM, Sky Flyer via llvm-dev wrote:
> It seems like d0 is always 14!
> I check it with ARMGenAsmMatcher.inc it was the same!
> How is it possible? because it should give the same register value that
> matches the underlying platform not any autogenerated value!?
The returned number is the register id as defined in
<YourTarget>GenRegisterInfo.inc. These numbers