search for: htotal

...rom rounding issues. > > So to me these all look like code that someone should fix regardless. OK, so I went ahead a wrote a bit of cocci [1] to find the bad apples. Unfortunately it found a lot of strange stuff: panel-sony-acx424akp.c:51/sony_acx424akp_vid_mode: 60 vs. 727 (.clock=330000 .htotal=480 + 15 + 0 + 15 .vtotal=864 + 14 + 1 + 11) panel-sony-acx424akp.c:71/sony_acx424akp_cmd_mode: 60 vs. 711 (.clock=420160 .htotal=480 + 154 + 16 + 32 .vtotal=864 + 1 + 1 + 1) panel-ilitek-ili9322.c:543/srgb_320x240_mode: 60 vs. 10168 (.clock=2453500 .htotal=320 + 359 + 1 + 241 .vtotal=262) panel-il...

On Tue, Feb 25, 2020 at 04:19:27PM +0100, Andrzej Hajda wrote: > On 25.02.2020 12:21, Ville Syrj?l? wrote: > > On Mon, Feb 24, 2020 at 03:14:54PM +0100, Andrzej Hajda wrote: > >> On 19.02.2020 21:35, Ville Syrjala wrote: > >>> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > >>> > >>> Get rid of mode->vrefresh and just

...(II) NVIDIA(0): (II) NVIDIA(0): --- Building ModePool for DFP-0 --- (II) NVIDIA(0): (II) NVIDIA(0): Native backend timings for DFP-0: (II) NVIDIA(0): 640 x 480 @ 60 Hz (II) NVIDIA(0): Pixel Clock : 25.175 MHz (II) NVIDIA(0): HRes, HSyncStart : 640, 656 (II) NVIDIA(0): HSyncEnd, HTotal : 752, 800 (II) NVIDIA(0): VRes, VSyncStart : 480, 490 (II) NVIDIA(0): VSyncEnd, VTotal : 492, 525 (II) NVIDIA(0): H/V Polarity : -/- (II) NVIDIA(0): (II) NVIDIA(0): Validating Mode "1920x1080": (II) NVIDIA(0): 1920 x 1080 @ 60 Hz (II) NVIDIA(0): Mode Sourc...

Hi, Here I post these 2 misc patches. Best regards, Maxim Levitsky

...s, u32 offset) tmp &= 0x7f; tmp |= (addr >> 12) & 0x80; wreg_crt(cirrus, 0x1d, tmp); + + drm_dev_exit(idx); } static int cirrus_mode_set(struct cirrus_device *cirrus, @@ -176,9 +182,12 @@ static int cirrus_mode_set(struct cirrus_device *cirrus, { int hsyncstart, hsyncend, htotal, hdispend; int vtotal, vdispend; - int tmp; + int tmp, idx; int sr07 = 0, hdr = 0; + if (!drm_dev_enter(&cirrus->dev, &idx)) + return -1; + htotal = mode->htotal / 8; hsyncend = mode->hsync_end / 8; hsyncstart = mode->hsync_start / 8; @@ -264,6 +273,7 @@ static int...

Hi, Here is my patch queue I accumulated over quite a long time. Patches 1-6 are bugfixes, and rest is mostly RFC. Comments are welcome. Best regards, Maxim Levitsky

...; + addr = offset >> 2; wreg_crt(cirrus, 0x0c, (u8)((addr >> 8) & 0xff)); wreg_crt(cirrus, 0x0d, (u8)(addr & 0xff)); @@ -179,6 +182,9 @@ static int cirrus_mode_set(struct cirrus_device *cirrus, int tmp; int sr07 = 0, hdr = 0; + if (!cirrus->mmio) + return -1; + htotal = mode->htotal / 8; hsyncend = mode->hsync_end / 8; hsyncstart = mode->hsync_start / 8; @@ -301,6 +307,9 @@ static int cirrus_fb_blit_rect(struct drm_framebuffer *fb, struct cirrus_device *cirrus = fb->dev->dev_private; void *vmap; + if (!cirrus->vram) + return -ENODEV;...

...s, u32 offset) tmp &= 0x7f; tmp |= (addr >> 12) & 0x80; wreg_crt(cirrus, 0x1d, tmp); + + drm_dev_exit(idx); } static int cirrus_mode_set(struct cirrus_device *cirrus, @@ -176,9 +182,12 @@ static int cirrus_mode_set(struct cirrus_device *cirrus, { int hsyncstart, hsyncend, htotal, hdispend; int vtotal, vdispend; - int tmp; + int tmp, idx; int sr07 = 0, hdr = 0; + if (!drm_dev_enter(&cirrus->dev, &idx)) + return -1; + htotal = mode->htotal / 8; hsyncend = mode->hsync_end / 8; hsyncstart = mode->hsync_start / 8; @@ -264,6 +273,7 @@ static int...

...+{ + int convert_cpp = cirrus_convert_to(fb); + + if (convert_cpp) + return convert_cpp * fb->width; + return fb->pitches[0]; +} + +static int cirrus_mode_set(struct cirrus_device *cirrus, + struct drm_display_mode *mode, + struct drm_framebuffer *fb) +{ + int hsyncstart, hsyncend, htotal, hdispend; + int vtotal, vdispend; + int tmp; + int sr07 = 0, hdr = 0; + + htotal = mode->htotal / 8; + hsyncend = mode->hsync_end / 8; + hsyncstart = mode->hsync_start / 8; + hdispend = mode->hdisplay / 8; + + vtotal = mode->vtotal; + vdispend = mode->vdisplay; + + vdispend -= 1;...

...drivers/gpu/drm/mcde/mcde_dsi.c > +++ b/drivers/gpu/drm/mcde/mcde_dsi.c > @@ -538,7 +538,7 @@ static void mcde_dsi_setup_video_mode(struct mcde_dsi *d, > */ > /* (ps/s) / (pixels/s) = ps/pixels */ > pclk = DIV_ROUND_UP_ULL(1000000000000, > - (mode->vrefresh * mode->htotal * mode->vtotal)); > + (drm_mode_vrefresh(mode) * mode->htotal * mode->vtotal)); > dev_dbg(d->dev, "picoseconds between two pixels: %llu\n", > pclk); > This just caught my eye while browsing the patch. It looks like a backward way to get the clock. But p...

...rm/nouveau/dispnv04/tvnv17.c @@ -209,6 +209,8 @@ static int nv17_tv_get_ld_modes(struct drm_encoder *encoder, struct drm_display_mode *mode; mode = drm_mode_duplicate(encoder->dev, tv_mode); + if (!mode) + continue; mode->clock = tv_norm->tv_enc_mode.vrefresh * mode->htotal / 1000 * -- 2.37.2

...\ > + > + > +static int cirrus_mode_set(struct cirrus_device *cirrus, > + struct drm_crtc_state *crtc_state) > +{ > + struct drm_display_mode *mode = &crtc_state->mode; > + int hsyncstart, hsyncend, htotal, hdispend; > + int vtotal, vdispend; > + int tmp; > + int sr07 = 0, hdr = 0; > + > + htotal = mode->htotal / 8; > + hsyncend = mode->hsync_end / 8; > + hsyncstart = mode->hsync_start / 8; > + hdispend = mode->hdisplay / 8...

...G8(VGA_DAC_MASK); \ + RREG8(VGA_DAC_MASK); \ + WREG8(VGA_DAC_MASK, v); \ + } while (0) \ + + +static int cirrus_mode_set(struct cirrus_device *cirrus, + struct drm_crtc_state *crtc_state) +{ + struct drm_display_mode *mode = &crtc_state->mode; + int hsyncstart, hsyncend, htotal, hdispend; + int vtotal, vdispend; + int tmp; + int sr07 = 0, hdr = 0; + + htotal = mode->htotal / 8; + hsyncend = mode->hsync_end / 8; + hsyncstart = mode->hsync_start / 8; + hdispend = mode->hdisplay / 8; + + vtotal = mode->vtotal; + vdispend = mode->vdisplay; + + vdispend -= 1;...

...G8(VGA_DAC_MASK); \ + RREG8(VGA_DAC_MASK); \ + WREG8(VGA_DAC_MASK, v); \ + } while (0) \ + + +static int cirrus_mode_set(struct cirrus_device *cirrus, + struct drm_crtc_state *crtc_state) +{ + struct drm_display_mode *mode = &crtc_state->mode; + int hsyncstart, hsyncend, htotal, hdispend; + int vtotal, vdispend; + int tmp; + int sr07 = 0, hdr = 0; + + htotal = mode->htotal / 8; + hsyncend = mode->hsync_end / 8; + hsyncstart = mode->hsync_start / 8; + hdispend = mode->hdisplay / 8; + + vtotal = mode->vtotal; + vdispend = mode->vdisplay; + + vdispend -= 1;...

...b, tmp); + + tmp = rreg_crt(cirrus, 0x1d); + tmp &= 0x7f; + tmp |= (addr >> 12) & 0x80; + wreg_crt(cirrus, 0x1d, tmp); +} + +static int cirrus_mode_set(struct cirrus_device *cirrus, + struct drm_display_mode *mode, + struct drm_framebuffer *fb) +{ + int hsyncstart, hsyncend, htotal, hdispend; + int vtotal, vdispend; + int tmp; + int sr07 = 0, hdr = 0; + + htotal = mode->htotal / 8; + hsyncend = mode->hsync_end / 8; + hsyncstart = mode->hsync_start / 8; + hdispend = mode->hdisplay / 8; + + vtotal = mode->vtotal; + vdispend = mode->vdisplay; + + vdispend -= 1;...

...- printk(KERN_INFO "hdisplay is %d\n", mode->hdisplay); - printk(KERN_INFO "vdisplay is %d\n", mode->vdisplay); - printk(KERN_INFO "HSS is %d\n", mode->hsync_start); - printk(KERN_INFO "HSE is %d\n", mode->hsync_end); - printk(KERN_INFO "htotal is %d\n", mode->htotal); - printk(KERN_INFO "VSS is %d\n", mode->vsync_start); - printk(KERN_INFO "VSE is %d\n", mode->vsync_end); - printk(KERN_INFO "vtotal is %d\n", mode->vtotal); - printk(KERN_INFO "clock is %d\n", mode->clock); +...

...drivers/gpu/drm/mcde/mcde_dsi.c > +++ b/drivers/gpu/drm/mcde/mcde_dsi.c > @@ -538,7 +538,7 @@ static void mcde_dsi_setup_video_mode(struct mcde_dsi *d, > */ > /* (ps/s) / (pixels/s) = ps/pixels */ > pclk = DIV_ROUND_UP_ULL(1000000000000, > - (mode->vrefresh * mode->htotal * mode->vtotal)); > + (drm_mode_vrefresh(mode) * mode->htotal * mode->vtotal)); Shouldn't you just use the pixel clock here ? Update: There's a patch further in this series that handles this, great :-) > dev_dbg(d->dev, "picoseconds between two pixels: %llu\n&...

..."hdisplay is %d\n", mode->hdisplay); > - printk(KERN_INFO "vdisplay is %d\n", mode->vdisplay); > - printk(KERN_INFO "HSS is %d\n", mode->hsync_start); > - printk(KERN_INFO "HSE is %d\n", mode->hsync_end); > - printk(KERN_INFO "htotal is %d\n", mode->htotal); > - printk(KERN_INFO "VSS is %d\n", mode->vsync_start); > - printk(KERN_INFO "VSE is %d\n", mode->vsync_end); > - printk(KERN_INFO "vtotal is %d\n", mode->vtotal); > - printk(KERN_INFO "clock is %d\n",...

Update the cirrus driver to follow current best practices. While the driver's hardware is obsolete, the cirrus driver is still one of the go-to modules to learn about writing a DRM driver. So keep it in good shape. Patches 1 to 3 simplify blitting and convert it to the DRM's current helpers. Patches 4 to 8 replace simple-KMS helpers with DRM's regular atomic helpers. The former are

...jeto "OPTIONS" n?o encontrado Looking for OPTIONS in the code I found that this need a P.limit in an OPTIONS object. I make it. > OPTIONS <- NULL > OPTIONS$P.limit <- 0.05 > m.pres.step <- grasp.step.anova(m.pres,scope=list(upper=~(ProfSer+NgalhoSer+CTOTAL+DensRamos+Htotal+CAP)^3,lower=~1),trace=1,direction="both") # # FUNCTION: grasp.step.anova # (by Splus, adapted by A. Lehmann from step.gam) # grasp.step.anova is a modified version of step.gam of Splus using ANOVA based on Chi or F tests instead # of AIC criteria # Erro em untangle.scope(object$t...