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On Jan 3, 2014, at 11:01 AM, Andrew Trick <atrick at apple.com> wrote: > > On Jan 3, 2014, at 4:58 AM, Haishan <hndxvon at 163.com> wrote: > >> >> At 2014-01-01 04:36:21,"Andrew Trick" <atrick at apple.com> wrote: >> >> On Dec 31, 2013, at 3:52 AM, Haishan <hndxvon at 163.com> wrote: >> My update steps are shown following: >> LiveIntervals *LIS =...

At 2014-01-01 04:36:21,"Andrew Trick" <atrick at apple.com> wrote: On Dec 31, 2013, at 3:52 AM, Haishan <hndxvon at 163.com> wrote: Hi, I insert a new machine basic block(MBB) before Greedy Register Allocation, after Simple Register Coalescing. But I encounter a fatal error "regalloc = ... not currently supported with -O0". I use command line with opt level O2, not O0. The probable reason of...

...at apple.com> wrote: > > On Jan 3, 2014, at 12:10 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > >> >> On Jan 3, 2014, at 11:01 AM, Andrew Trick <atrick at apple.com> wrote: >> >>> >>> On Jan 3, 2014, at 4:58 AM, Haishan <hndxvon at 163.com> wrote: >>> >>>> >>>> At 2014-01-01 04:36:21,"Andrew Trick" <atrick at apple.com> wrote: >>>> >>>> On Dec 31, 2013, at 3:52 AM, Haishan <hndxvon at 163.com> wrote: >>>> My update steps are...

On Jan 4, 2014, at 4:38 AM, Haishan <hndxvon at 163.com> wrote: > At 2014-01-04 06:11:38,"Jakob Stoklund Olesen" <stoklund at 2pi.dk> wrote: > > On Jan 3, 2014, at 1:52 PM, Andrew Trick <atrick at apple.com> wrote: > >> He really just wants to rerun LiveIntervals analysis, but LiveVariables is no...

...pass. If you want to do it in the selection DAG, there is a subtarget hook that might do it: TargetSubtargetInfo::useAA() LLVM won’t generate the schedule you want anyway for Intel core processors, but the alias analysis can be useful in general. -Andy On Dec 16, 2013, at 6:03 AM, Haishan <hndxvon at 163.com> wrote: > At 2013-12-15 22:43:34,"Caldarale, Charles R" <Chuck.Caldarale at unisys.com> wrote: > >> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > >> On Behalf Of Haishan > >> Subject: [LLVMdev] Question ab...

Hi, I have implemented a pair intrinsic nodes in back-end, But there is a chain dependence between two intrinsic nodes. So in the Pre-RA-sched stage, these two intrinsic nodes would be apart. I expect that there is no node between these two intrinsic nodes, therefore, I guess it would be work if there is a MVT::Glue between these nodes. But I don’t know how to add. Thanks in advance. Haishan

At 2013-12-15 22:43:34,"Caldarale, Charles R" <Chuck.Caldarale at unisys.com> wrote: >> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] >> On Behalf Of Haishan >> Subject: [LLVMdev] Question about Pre-RA-schedule in LLVM3.3 > >> My clang version is 3.3 and debug build. > >> //test.c >> int a[6] = {1, 2, 3, 4, 5,

Hi, I insert a new machine basic block(MBB) before Greedy Register Allocation, after Simple Register Coalescing. But I encounter a fatal error "regalloc = ... not currently supported with -O0". I use command line with opt level O2, not O0. The probable reason of this error is that no LiveInterval information for newly MBB which is used by Register Allocation. And, LiveIntervals depend

...someone considered coding/porting target-indenpent SMS in latest version of LLVM? Or have any suggestion for porting these code? Best Wishes -Haishan At 2013-12-13 01:35:01,"James Courtier-Dutton" <james.dutton at gmail.com> wrote: >On 12 December 2013 13:58, Haishan <hndxvon at 163.com> wrote: >> Hi, >> I try to add a backend (machine function) pass in LLVM 3.3 source code. >> In order to analyse precise information of machine instructions, I need some >> information of >> IR instruction which corresponds to MachineInstrs. If so, it...

On Jan 3, 2014, at 1:52 PM, Andrew Trick <atrick at apple.com> wrote: > He really just wants to rerun LiveIntervals analysis, but LiveVariables is no longer available. Would it work just to clear all the intervals rerun LiveIntervals::computeVirtRegs after all the CFG transforms are complete? Yes, I should think so. /jakob -------------- next part -------------- An HTML attachment was

hello,everyone recently, I analyze the compiler optimization level, so I have searched the usage of profile-guided optimization of LLVM, but little result in google, therefore, could you please list detailed usage of profile-guided optimization? LLVM must be install with flags '--enable-profile'? A example will be pleasure. thanks von -------------- next part -------------- An HTML

Hi Tim, Firstly, thanks for your reply. I agree on your idea about integer overflow in this test. But, in fact, the content of this test is the same to gcc\testsuite\gcc.c-torture\execute\920612-1.c. gcc can handle it correctly. Moreover, when I compile this test using clang with optlevel O0 instead of O2. Its execution result is the same to gcc. That to say, for this test, clang with optlevel

Hi, I try to add a backend (machine function) pass in LLVM 3.3 source code. In order to analyse precise information of machine instructions, I need some information of IR instruction which corresponds to MachineInstrs. If so, it's much easier to analyse IR Instructions instead of MachineInstrs. However, in the frame of LLVM 3.3, I can't find the corresponding(connected) information from

hi, I compile a case (test.c) to get IR file (test.ll) using clang as follows: "clang -emit-llvm -S -O2 test.c -o test.ll" My clang source code version is release 3.3 and debugging build. //test.c int foo(int j) { return ++j > 0; } int main() { if (foo(((~0U)>>1))) abort(); exit(0) } //end test.c Here are the generated IR file: //test.ll ;

hi, I have few question about breaking anti-dependence of postRAScheduler in LLVM. when I use command line "clang -target arm -mcpu=cortex-a8 -O2 -integrated-as -c test.c -o test.o" and get objdump file as follows: ldrr1, [r0,#16]----(1 str r1, [r0,#32]----(2 ldr r1, [r0,#12]----(3 str r1, [r0,#36]----(4 ldr r1, [r0,#08]----(5 str r1, [r0,#40]----(6 However, I expect that instruction

Hi, I compile a case (test.c) to get object machine file (test.o) using clang as follows: "clang -target arm -integrated-as -c test.c -o test.o" My clang version is 3.3 and debug build. //test.c int a[6] = {1, 2, 3, 4, 5, 6} int main() { a[0] = a[5]; a[1] = a[4]; a[2] = a[5]; } //end test.c Then test.dump is generated by using the objdump tool. //test.dump ldr r1, [r0, #20]