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...similar work like basicblockprofiling, of course based on llvm. Blow is the project information: http://formes.asia/cms/ -- Best Regards, Zhang Zuyu(张祖羽) ----------------------------------------------------------- College of Computer Science and Technology, Harbin Engineering University Email: hitzzy at gmail.com QQ: 339753431 Gtalk: hitzzy at gmail.com -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20101015/02446044/attachment.html> -------------- next part -------------- A non-text attachment was scru...

On Fri, Dec 2, 2011 at 4:07 PM, Rahil Rahimian <rahil_rahimian at yahoo.com>wrote: > Hi , > > I want to create a bc file by llvm-gcc, and need to pass a input file when > create this file, > how can i do it?I saw options in "*llvm-gcc* [*options*] *filename" but > it could not help me.* > > llvm-gcc -emit-llvm -c foo.c -o foo.bc > ** > *I have an

Hi , I want to create a bc file by llvm-gcc, and need to pass a input file when create this file, how can i do it?I saw options in "llvm-gcc [options] filename" but it could not help me. I have an another problem too. my program contains some C file , that main function use those, but i don't know how create bc file with regard to other file.  tanks, -------------- next part

On Tue, Sep 6, 2011 at 9:34 PM, Alexandru Dura <alexdura at gmail.com> wrote: > Hi everyone, > > I found some peculiar behavior of TableGen when generating > [TARGET]GenRegisterInfo.inc. Some register overlaps are generated twice in > this file, leading to a compilation error. Hi, What do you mean "overlapped register"? > I think this is because in

Hi everyone, I found some peculiar behavior of TableGen when generating [TARGET]GenRegisterInfo.inc. Some register overlaps are generated twice in this file, leading to a compilation error. I think this is because in RegisterInfoEmitter.cpp, RegisterAliases are declared as "std::map<Record*, std::set<Record*>, LessRecord>" and a requirement for std::map is that the

Hi LLVMers, I'm writing a LLVM backend for C*Core, an ISA derived from Motorola M*Core. I was wondering if someone wrote some IR level optimization passes for backend porting before ISel, such as an IR transformation from GEP to integer conversion/calculating instructions, and PHI combination. Here's the bubble sorting example. The IR codes below are changed by hand and I try to write

Hi, all: Now I'm working on writing a backend for Moto MCore, but I don't know how to describe some instructions. First, I've already written MCoreRegisterInfo.td like these: class MCoreReg<bits<4> num, string name> : Register<name> { let Namespace = "MCore"; field bits<4> Num = num; } def R0 : MCoreReg< 0, "R0">,