Displaying 5 results from an estimated 5 matches for "hefr".
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2011 Oct 02
7
[LLVMdev] LLVM and VHDL simulation
Hi,
I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process.
To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This
2011 Oct 06
0
[LLVMdev] MIPS 32bit code generation
...stem for all the
> llvm projects is svn, I'd just as soon use svn as the tool at my end.
The git mirrors only contain what's in trunk in the SVN repos.
// Oliver
------------------------------
Message: 11
Date: Thu, 6 Oct 2011 09:32:21 +0000
From: Baggett Jonas <Jonas.Baggett at hefr.ch>
Subject: [LLVMdev] TR : LLVM and VHDL simulation
To: "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu>
Message-ID:
<D2D188690F92F64B81201CA7EA90831A01F05446 at HEFRMBX01.sofr.hefr.lan>
Content-Type: text/plain; charset="us-ascii"
Thanks for your answ...
2011 Oct 06
0
[LLVMdev] LLVM and VHDL simulation
On Sun, Oct 2, 2011 at 4:24 PM, Baggett Jonas <Jonas.Baggett at hefr.ch> wrote:
> Hi,
>
> I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process.
> To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that...
2011 Oct 06
0
[LLVMdev] TR : LLVM and VHDL simulation
Thanks for your answers.
In one year, I am going to have something like a semester project.
The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the time to do a full VHDL
2011 Oct 10
0
[LLVMdev] Vlang - TR : LLVM and VHDL simulation
Hi Pavel,
> If you are interested in HDLs perhaps you would be interested in Vlang?
> I am currently working on Verilog fronted and I am looking for somebody with
> VHDL interest to join the Vlang project.
I have never heard about the Vlang project but it seems to be an interesting project. I think I
could be interested to join this project and do the VHDL front-end.
However, there are