Displaying 10 results from an estimated 10 matches for "hastailcall".
Did you mean:
hadtailcall
2016 Mar 30
2
Instruction selection pattern for intrinsic returning llvm_any_ty
..., i16 %_tmp2)
and then the return value struct is lowered to two i16:s by
SelectionDAGISel::SelectBasicBlock:
// Lower the instructions. If a call is emitted as a tail call, cease
emitting
// nodes for this block.
for (BasicBlock::const_iterator I = Begin; I != End &&
!SDB->HasTailCall; ++I)
SDB->visit(*I);
just prior to the selection.
> I’m also not sure if tablegen currently supports patterns with multiple results
Yes, me neither...
/Mikael
>
> -Matt
>
2010 Aug 27
0
[LLVMdev] What does this error mean: psuedo instructions should be removed before code emission?
On Aug 27, 2010, at 3:43 PMPDT, Yuri wrote:
> On 08/27/2010 12:13, Dale Johannesen wrote:
> Here's what happens:
> The first instruction created is RET.
> SelectBasicBlock is called.
> TCRETURNri64 is created from within it.
> HasTailCall is set to true as you mentioned.
> Cycle in SelectionDAGISel::SelectBasicBlock skips the rest.
>
> All like you described. But the RET instruction still stays in the
> end.
> RET is skipped by visit but I guess stays in the list. Where should
> it be destroyed?
Ahh, this is...
2010 Aug 27
2
[LLVMdev] What does this error mean: psuedo instructions should be removed before code emission?
...ming RET (the Instruction, not the MachineInstr)
> is not getting skipped for some reason. I suggest stepping through
> the path above to figure out why.
>
Here's what happens:
The first instruction created is RET.
SelectBasicBlock is called.
TCRETURNri64 is created from within it.
HasTailCall is set to true as you mentioned.
Cycle in SelectionDAGISel::SelectBasicBlock skips the rest.
All like you described. But the RET instruction still stays in the end.
RET is skipped by visit but I guess stays in the list. Where should it
be destroyed?
Yuri
2016 Mar 30
0
Instruction selection pattern for intrinsic returning llvm_any_ty
...pes that expand into a struct would be more normal
>
> SelectionDAGISel::SelectBasicBlock:
>
> // Lower the instructions. If a call is emitted as a tail call, cease emitting
> // nodes for this block.
> for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
> SDB->visit(*I);
>
> just prior to the selection.
>
>> I’m also not sure if tablegen currently supports patterns with multiple results
>
> Yes, me neither...
>
> /Mikael
>
>>
>> -Matt
-------------- next part --------------
An HTML at...
2016 Mar 30
0
Instruction selection pattern for intrinsic returning llvm_any_ty
> On Mar 30, 2016, at 11:43, Mikael Holmén <mikael.holmen at ericsson.com> wrote:
>
> Hi,
>
> On 03/30/2016 11:38 AM, Matt Arsenault wrote:
>>
>>> On Mar 30, 2016, at 11:35, Mikael Holmén <mikael.holmen at ericsson.com
>>> <mailto:mikael.holmen at ericsson.com>> wrote:
>>>
>>> i16 (divm16_pseudo …)
>>>
2016 Mar 30
2
Instruction selection pattern for intrinsic returning llvm_any_ty
Hi,
On 03/30/2016 11:38 AM, Matt Arsenault wrote:
>
>> On Mar 30, 2016, at 11:35, Mikael Holmén <mikael.holmen at ericsson.com
>> <mailto:mikael.holmen at ericsson.com>> wrote:
>>
>> i16 (divm16_pseudo …)
>>
>> stuff?
>>
>> I've tried
>> (i16, i16 (divm16_pseudo i16:$src1, i16:$src2)
>> and
>> ((i16, i16)
2011 Jun 06
0
[LLVMdev] Understanding SelectionDAG construction
Hi Ankur,
> The flags "-view-sched-dags".. described in the doc doesn't seem to work. (
> "llc -help" doesn't list it ).
as far as I remember, displaying DAGs during compilation is only enabled
in "debug builds" [1] of LLVM. You probably have to re-configure and
re-compile LLVM to enable this feature.
Best regards,
Christoph
[1]
2010 Aug 27
0
[LLVMdev] What does this error mean: psuedo instructions should be removed before code emission?
On Aug 27, 2010, at 11:53 AMPDT, Yuri wrote:
> On 08/27/2010 11:32, Yuri wrote:
>> As I understand only one of TCRETURNri64 and RET should be created.
>> I have sources of rev.112200.
>>
>> Here is the stack when TCRETURNri64 instruction is created:
>> #1 0x0000000802c8b4e2 in llvm::MachineFunction::CreateMachineInstr
>> (this=0x30eb000, TID=@0x803a78940,
2011 Jun 06
4
[LLVMdev] Understanding SelectionDAG construction
I am trying to understand the SelectionDAG construction from LLVM IR. I have
gone through the doc "The LLVM Target-Independent Code Generator" on LLVM
site. This gives a great initial overview. However I am unable to catch the
actual control flow for the llvm->selectionDag conversion.
The flags "-view-sched-dags".. described in the doc doesn't seem to work. (
"llc
2010 Aug 27
2
[LLVMdev] What does this error mean: psuedo instructions should be removed before code emission?
On 08/27/2010 11:32, Yuri wrote:
> As I understand only one of TCRETURNri64 and RET should be created.
> I have sources of rev.112200.
>
> Here is the stack when TCRETURNri64 instruction is created:
> #1 0x0000000802c8b4e2 in llvm::MachineFunction::CreateMachineInstr
> (this=0x30eb000, TID=@0x803a78940, DL={LineCol = 0, ScopeIdx = 0},
> NoImp=false) at