search for: halfwords

Hi all, when compiling code like short ptr * = some_address; int val; val = *ptr; if (val>2047) val = 2047; else if (val<-2048) val = -2048. // other things done that require val to be an int ... The load operation is represented by a load and a sign extension operation in the LLVM IR. On most target architectures, there exist signed halfword load instructions, so the load and

done, bug 15057, hope I submitted it correctly ... On 23 Jan 2013, at 22:29, Arnold Schwaighofer <aschwaighofer at apple.com> wrote: > Hi Bjorn, > > could you file a bug on llvm.org/bugs and cc me on it. > > Thanks, > Arnold > > >> So it appears that also the ARM backend has a big problems with sign-extending loads. >> >> I've compiled the

Hi Bjorn, could you file a bug on llvm.org/bugs and cc me on it. Thanks, Arnold > So it appears that also the ARM backend has a big problems with sign-extending loads. > > I've compiled the following loop > > short in[]; > int out[]; > int value; > > for (i = 0; i < nr; i++) { > value = in[i]; > if (value>2047) >

Instruction selection happens on a different IR: SelectionDAG. In this IR, there are sign-extending loads that the IR converter will use, and are used for example to load 8/16-bit values into 32-bit registers (with sign or zero extension). Any optimizations performed during codegen will be in this representation, or even MachineInstr form, which is post-isel and any sign-extension information

Commit-ID: 59f3f33338f371b3a30163406fbb5fe323503939 Gitweb: http://git.kernel.org/?p=libs/klibc/klibc.git;a=commit;h=59f3f33338f371b3a30163406fbb5fe323503939 Author: James Cowgill <james.cowgill at mips.com> AuthorDate: Fri, 2 Mar 2018 08:33:02 -0800 Committer: Ben Hutchings <ben at decadent.org.uk> CommitDate: Wed, 2 Jan 2019 03:08:04 +0000 [klibc] mips/mips64: simplify

Commit-ID: 3438d861da2e6939a6b0d454ffe247c19ead5993 Gitweb: http://git.kernel.org/?p=libs/klibc/klibc.git;a=commit;h=3438d861da2e6939a6b0d454ffe247c19ead5993 Author: Dejan Latinovic <Dejan.Latinovic at imgtec.com> AuthorDate: Thu, 5 Mar 2015 16:51:45 -0800 Committer: H. Peter Anvin <hpa at linux.intel.com> CommitDate: Thu, 5 Mar 2015 16:51:45 -0800

On Mon, Jan 21, 2013 at 9:16 AM, Bjorn De Sutter < bjorn.desutter at elis.ugent.be> wrote: > On 21 Jan 2013, at 14:39, Justin Holewinski <justin.holewinski at gmail.com> > wrote: > > Instruction selection happens on a different IR: SelectionDAG. In this > IR, there are sign-extending loads that the IR converter will use, and are > used for example to load 8/16-bit

On 21 Jan 2013, at 14:39, Justin Holewinski <justin.holewinski at gmail.com> wrote: > Instruction selection happens on a different IR: SelectionDAG. In this IR, there are sign-extending loads that the IR converter will use, and are used for example to load 8/16-bit values into 32-bit registers (with sign or zero extension). Any optimizations performed during codegen will be in this

On Jan 21, 2013, at 6:34 AM, Justin Holewinski <justin.holewinski at gmail.com> wrote: > > On Mon, Jan 21, 2013 at 9:16 AM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > On 21 Jan 2013, at 14:39, Justin Holewinski <justin.holewinski at gmail.com> wrote: > >> Instruction selection happens on a different IR: SelectionDAG. In this IR, there are

We already divided out our classes as you did for ARM. The problem here is that we have a store/load byte/halfword to/from a Frame object. We know at that time that it's not going to be possible to store it using SP because there is only such instructions for store/load of a word. What we would want to do is to move SP into a Mips 16 register and then do a indexed load/store off of that

Ok. That's a somewhat different problem, then. Devil will be in the details of what you want to do. A few options. First is to always have a standard frame pointer register available and reference off of that. Caveat: dynamic stack realignment and vararrays muck with that more than a bit. Second is what gcc is doing and reserve a register just for this in addition to the frame register.

Hello All, When going through the Ogg format, I have a basic question. As per the RFC the Ogg format encapsulates the logical stream. Now consider the scenario where a raw mono stream is being encoded with Opus Codec. The stream is 48KHz and the length of the stream being encoded is worth 20ms of data. This makes it 960 half words (considering 16 bit format). Now if the final output is say 100

Trying to think of a clever way to do something.... On Mips 16, the SP (stack pointer) is not a directly accessible register in most instructions. There is a way to move to and from mips 16 registers (subset of mips32) and mips32 registers. For the load/store word instructions, there are forms which implicitly take SP. However, for store/load byte and store/load halfword, there is no such

Actually, SP is already not in the mips 16 register class but there is some C++ code that is common to mips32, mips64 and mips16 that is wanting to use SP. It's kind of awkward but does work except in this case of load/store haflword and byte to stack objects. Maybe I'm shooting myself in the foot there. I don't know that code too well so maybe I need to look into it. There are

Hi llvm developers, I might be overlooking something, but I think the ARMConstantIsland pass uses the wrong size for the MachineInstrs representing jump tables: Currently, there is the following calculation in doInitialJumpTablePlacement (lib/Target/ARM/ARMConstantIslandPass.cpp:588): ---------------------------------------------------------------------- unsigned Size = JT[JTI].MBBs.size() *

On Wed, Sep 16, 2015 at 01:50:08PM +0530, Sudip Mukherjee wrote: > Hi, > While crosscompiling the kernel for openrisc with allmodconfig the build > failed with the error: > drivers/vhost/vhost.c: In function 'vhost_vring_ioctl': > drivers/vhost/vhost.c:818:3: error: call to '__compiletime_assert_818' declared with attribute error: BUILD_BUG_ON failed: __alignof__

Hi, While crosscompiling the kernel for openrisc with allmodconfig the build failed with the error: drivers/vhost/vhost.c: In function 'vhost_vring_ioctl': drivers/vhost/vhost.c:818:3: error: call to '__compiletime_assert_818' declared with attribute error: BUILD_BUG_ON failed: __alignof__ *vq->avail > VRING_AVAIL_ALIGN_SIZE Can you please give me any idea about what the

Hi, While crosscompiling the kernel for openrisc with allmodconfig the build failed with the error: drivers/vhost/vhost.c: In function 'vhost_vring_ioctl': drivers/vhost/vhost.c:818:3: error: call to '__compiletime_assert_818' declared with attribute error: BUILD_BUG_ON failed: __alignof__ *vq->avail > VRING_AVAIL_ALIGN_SIZE Can you please give me any idea about what the

...es: one for the identification header (OpusHead), which must contain only that packet, one (or more) for the metadata header (OpusTags), which must terminate the page it ends on, and then one more for your 20 ms audio data packet. In the description, you also said that the final output was 100 halfwords (200 bytes). The value in the page segment table is the number of bytes, not the number of halfwords. > If the above is true then if the Page Segment has the value 20, then the > segment table shall look something like (assuming 100 half words is what > is encoded evry time) > > 10...

...identification header (OpusHead), which must contain only that packet, one > (or more) for the metadata header (OpusTags), which must terminate the page > it ends on, and then one more for your 20 ms audio data packet. > > In the description, you also said that the final output was 100 halfwords > (200 bytes). The value in the page segment table is the number of bytes, > not the number of halfwords. > > If the above is true then if the Page Segment has the value 20, then the >> segment table shall look something like (assuming 100 half words is what >> is encoded ev...