search for: halfword

...e_address; int val; val = *ptr; if (val>2047) val = 2047; else if (val<-2048) val = -2048. // other things done that require val to be an int ... The load operation is represented by a load and a sign extension operation in the LLVM IR. On most target architectures, there exist signed halfword load instructions, so the load and sign extension are effectively translated into a single instruction during instruction selection. Nonetheless, this sign extension operation in the IR prohibits a lot of optimizations: - it counts as an instruction in heuristics based on instruction counts (such...

done, bug 15057, hope I submitted it correctly ... On 23 Jan 2013, at 22:29, Arnold Schwaighofer <aschwaighofer at apple.com> wrote: > Hi Bjorn, > > could you file a bug on llvm.org/bugs and cc me on it. > > Thanks, > Arnold > > >> So it appears that also the ARM backend has a big problems with sign-extending loads. >> >> I've compiled the

Hi Bjorn, could you file a bug on llvm.org/bugs and cc me on it. Thanks, Arnold > So it appears that also the ARM backend has a big problems with sign-extending loads. > > I've compiled the following loop > > short in[]; > int out[]; > int value; > > for (i = 0; i < nr; i++) { > value = in[i]; > if (value>2047) >

...f (val>2047) > val = 2047; > else if (val<-2048) > val = -2048. > // other things done that require val to be an int ... > > The load operation is represented by a load and a sign extension operation > in the LLVM IR. On most target architectures, there exist signed halfword > load instructions, so the load and sign extension are effectively > translated into a single instruction during instruction selection. > Nonetheless, this sign extension operation in the IR prohibits a lot of > optimizations: > > - it counts as an instruction in heuristics based...

...s64/crt0.S index 775a919..3f1c2a9 100644 --- a/usr/klibc/arch/mips64/crt0.S +++ b/usr/klibc/arch/mips64/crt0.S @@ -10,22 +10,12 @@ #include <machine/asm.h> -NESTED(__start, 64, sp) - daddiu sp,sp,-64 - sd zero, 32(sp) - - # Initialize gp - lui gp,%highest(_gp) # load highest "halfword" - daddiu gp,gp,%higher(_gp) # merge next "halfword" - dsll gp,gp,16 # shift by one halfword - daddiu gp,gp,%hi(_gp) # merge next "halfword" - dsll gp,gp,16 # shift into final position - daddiu gp,gp,%lo(_gp) # merge lowest "halfword" - - daddiu a0, sp,...

...okes __libc_init +# with the appropriate arguments. +# +# See __static_init.c or __shared_init.c for the expected +# arguments. +# + +#include <machine/asm.h> + +NESTED(__start, 64, sp) + daddiu sp,sp,-64 + sd zero, 32(sp) + + # Initialize gp + lui gp,%highest(_gp) # load highest "halfword" + daddiu gp,gp,%higher(_gp) # merge next "halfword" + dsll gp,gp,16 # shift by one halfword + daddiu gp,gp,%hi(_gp) # merge next "halfword" + dsll gp,gp,16 # shift into final position + daddiu gp,gp,%lo(_gp) # merge lowest "halfword" + + daddiu a0, sp,...

...7; >> else if (val<-2048) >> val = -2048. >> // other things done that require val to be an int ... >> >> The load operation is represented by a load and a sign extension >> operation in the LLVM IR. On most target architectures, there exist signed >> halfword load instructions, so the load and sign extension are effectively >> translated into a single instruction during instruction selection. >> Nonetheless, this sign extension operation in the IR prohibits a lot of >> optimizations: >> >> - it counts as an instruction in h...

...t; if (val>2047) > val = 2047; > else if (val<-2048) > val = -2048. > // other things done that require val to be an int ... > > The load operation is represented by a load and a sign extension operation in the LLVM IR. On most target architectures, there exist signed halfword load instructions, so the load and sign extension are effectively translated into a single instruction during instruction selection. Nonetheless, this sign extension operation in the IR prohibits a lot of optimizations: > > - it counts as an instruction in heuristics based on instruction cou...

...> val = 2047; >> else if (val<-2048) >> val = -2048. >> // other things done that require val to be an int ... >> >> The load operation is represented by a load and a sign extension operation in the LLVM IR. On most target architectures, there exist signed halfword load instructions, so the load and sign extension are effectively translated into a single instruction during instruction selection. Nonetheless, this sign extension operation in the IR prohibits a lot of optimizations: >> >> - it counts as an instruction in heuristics based on instruc...

We already divided out our classes as you did for ARM. The problem here is that we have a store/load byte/halfword to/from a Frame object. We know at that time that it's not going to be possible to store it using SP because there is only such instructions for store/load of a word. What we would want to do is to move SP into a Mips 16 register and then do a indexed load/store off of that register.when...

...rame indices that are out of range. In addition to any of the above you may need something similar. On Sep 25, 2012, at 9:34 PM, Reed Kotler <rkotler at mips.com> wrote: > We already divided out our classes as you did for ARM. > > The problem here is that we have a store/load byte/halfword to/from a Frame object. > > We know at that time that it's not going to be possible to store it using SP because there is only such instructions for store/load of a word. > > What we would want to do is to move SP into a Mips 16 register and then do a indexed load/store off of th...

Hello All, When going through the Ogg format, I have a basic question. As per the RFC the Ogg format encapsulates the logical stream. Now consider the scenario where a raw mono stream is being encoded with Opus Codec. The stream is 48KHz and the length of the stream being encoded is worth 20ms of data. This makes it 960 half words (considering 16 bit format). Now if the final output is say 100

...(stack pointer) is not a directly accessible register in most instructions. There is a way to move to and from mips 16 registers (subset of mips32) and mips32 registers. For the load/store word instructions, there are forms which implicitly take SP. However, for store/load byte and store/load halfword, there is no such instruction. In such cases, if I were writing assembly language code, I would move SP to a mips 16 register and then use it to do the store/load byte/haflword. It also then becomes a common subexpression because there may be multiple such accesses. It's like a temporary...

...sible register in most instructions. >> There is a way to move to and from mips 16 registers (subset of mips32) and mips32 registers. >> >> For the load/store word instructions, there are forms which implicitly take SP. >> >> However, for store/load byte and store/load halfword, there is no such instruction. >> >> In such cases, if I were writing assembly language code, I would move SP to a mips 16 register and then use it to do the store/load byte/haflword. >> >> It also then becomes a common subexpression because there may be multiple such access...

...cpp:588): ---------------------------------------------------------------------- unsigned Size = JT[JTI].MBBs.size() * sizeof(uint32_t); ---------------------------------------------------------------------- Obviously, a size of 4 bytes per entry is incorrect for jump tables consisting of byte or halfword entries. Additionally, when trying to optimize for table size later in optimizeThumb2JumpTables, the opcode is updated without updating the size (lib/Target/ARM/ARMConstantIslandPass.cpp:2229): ---------------------------------------------------------------------- unsigned JTOpc = ByteOk ? ARM::J...

...ken. VRING_AVAIL_ALIGN_SIZE is 2 *vq->avail is: struct vring_avail { __virtio16 flags; __virtio16 idx; __virtio16 ring[]; }; And __virtio16 is just a u16 with some sparse annotations. Looking at openrisc architecture document: Operand: Length addr[3:0] if aligned Halfword (or half) 2 bytes Xxx0 Type C-TYPE Sizeof Alignment Openrisc Equivalent Short Signed short 2 2 Signed halfword and 16.1.2 Aggregates and Unions Aggregates (structures and arrays) and unions assume the alignment of their most strictly aligned element. So to me, it looks...

Hi, While crosscompiling the kernel for openrisc with allmodconfig the build failed with the error: drivers/vhost/vhost.c: In function 'vhost_vring_ioctl': drivers/vhost/vhost.c:818:3: error: call to '__compiletime_assert_818' declared with attribute error: BUILD_BUG_ON failed: __alignof__ *vq->avail > VRING_AVAIL_ALIGN_SIZE Can you please give me any idea about what the

Hi, While crosscompiling the kernel for openrisc with allmodconfig the build failed with the error: drivers/vhost/vhost.c: In function 'vhost_vring_ioctl': drivers/vhost/vhost.c:818:3: error: call to '__compiletime_assert_818' declared with attribute error: BUILD_BUG_ON failed: __alignof__ *vq->avail > VRING_AVAIL_ALIGN_SIZE Can you please give me any idea about what the

...es: one for the identification header (OpusHead), which must contain only that packet, one (or more) for the metadata header (OpusTags), which must terminate the page it ends on, and then one more for your 20 ms audio data packet. In the description, you also said that the final output was 100 halfwords (200 bytes). The value in the page segment table is the number of bytes, not the number of halfwords. > If the above is true then if the Page Segment has the value 20, then the > segment table shall look something like (assuming 100 half words is what > is encoded evry time) > > 1...

...identification header (OpusHead), which must contain only that packet, one > (or more) for the metadata header (OpusTags), which must terminate the page > it ends on, and then one more for your 20 ms audio data packet. > > In the description, you also said that the final output was 100 halfwords > (200 bytes). The value in the page segment table is the number of bytes, > not the number of halfwords. > > If the above is true then if the Page Segment has the value 20, then the >> segment table shall look something like (assuming 100 half words is what >> is encoded e...