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At 2013-12-15 22:43:34,"Caldarale, Charles R" <Chuck.Caldarale at unisys.com> wrote: >> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] >> On Behalf Of Haishan >> Subject: [LLVMdev] Question about Pre-RA-schedule in LLVM3.3 > >> My clang version is 3.3 and debug build. > >> //test.c >> int a[6] = {1, 2, 3, 4, 5, 6} >> int main() { >> a[0] = a[5]; >> a[1] = a[4]; >> a[2] = a[5]; >> } >> /...

On Jan 3, 2014, at 11:01 AM, Andrew Trick <atrick at apple.com> wrote: > > On Jan 3, 2014, at 4:58 AM, Haishan <hndxvon at 163.com> wrote: > >> >> At 2014-01-01 04:36:21,"Andrew Trick" <atrick at apple.com> wrote: >> >> On Dec 31, 2013, at 3:52 AM, Haishan <hndxvon at 163.com> wrote: >> My update steps are shown following: >> LiveInte...

At 2014-01-01 04:36:21,"Andrew Trick" <atrick at apple.com> wrote: On Dec 31, 2013, at 3:52 AM, Haishan <hndxvon at 163.com> wrote: Hi, I insert a new machine basic block(MBB) before Greedy Register Allocation, after Simple Register Coalescing. But I encounter a fatal error "regalloc = ... not currently supported with -O0". I use command line with opt level O2, not O0. The probab...

...ineScheduler pass. If you want to do it in the selection DAG, there is a subtarget hook that might do it: TargetSubtargetInfo::useAA() LLVM won’t generate the schedule you want anyway for Intel core processors, but the alias analysis can be useful in general. -Andy On Dec 16, 2013, at 6:03 AM, Haishan <hndxvon at 163.com> wrote: > At 2013-12-15 22:43:34,"Caldarale, Charles R" <Chuck.Caldarale at unisys.com> wrote: > >> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > >> On Behalf Of Haishan > >> Subject: [LLVMdev]...

...LiveVariables which require the machine function to be in SSA form. However, in this case, the modified machine function(including newly inserted MBB) is not SSA form any more. So, how to update LiveInterval information of newly MBB? Could someone help me with that? Thank you very much in advance. -Haishan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131231/eaf01df9/attachment.html>

...e between two intrinsic nodes. So in the Pre-RA-sched stage, these two intrinsic nodes would be apart. I expect that there is no node between these two intrinsic nodes, therefore, I guess it would be work if there is a MVT::Glue between these nodes. But I don’t know how to add. Thanks in advance. Haishan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140623/5cea9454/attachment.html>

...<atrick at apple.com> wrote: > > On Jan 3, 2014, at 12:10 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > >> >> On Jan 3, 2014, at 11:01 AM, Andrew Trick <atrick at apple.com> wrote: >> >>> >>> On Jan 3, 2014, at 4:58 AM, Haishan <hndxvon at 163.com> wrote: >>> >>>> >>>> At 2014-01-01 04:36:21,"Andrew Trick" <atrick at apple.com> wrote: >>>> >>>> On Dec 31, 2013, at 3:52 AM, Haishan <hndxvon at 163.com> wrote: >>>> My updat...

On Jan 4, 2014, at 4:38 AM, Haishan <hndxvon at 163.com> wrote: > At 2014-01-04 06:11:38,"Jakob Stoklund Olesen" <stoklund at 2pi.dk> wrote: > > On Jan 3, 2014, at 1:52 PM, Andrew Trick <atrick at apple.com> wrote: > >> He really just wants to rerun LiveIntervals analysis, but LiveVar...

...instruction are allocated same register. However, if we build a schedule graph like the following: I think that Pre-RA-sched has change to schedule apart load1 and store1, the same to load2 and store2. Have someone considered building such a schedule graph? Thank you very much if any suggestion. -Haishan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131215/3af945a6/attachment.html> -------------- next part -------------- A non-text attachment was scrubbed... Name: 截图2.png Type: image/png Size: 13552 byte...

...Error(E); It returns Error(E) . Then, the expression "foo(((~0U)>>1))" is optimized out in the later stage. Here FD is foo's function pointer, so I think it should not return Error. Maybe it is bug, could someone help me with that? Thanks a million in advance. --Haishan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131128/271832ba/attachment.html>

...ing Modulo Scheduling code updated by Tanya M.Latter in LLVM1.7 to LLVM3.3. And this map was used in the original SMS code of LLVM1.7. By the way, have you/someone considered coding/porting target-indenpent SMS in latest version of LLVM? Or have any suggestion for porting these code? Best Wishes -Haishan At 2013-12-13 01:35:01,"James Courtier-Dutton" <james.dutton at gmail.com> wrote: >On 12 December 2013 13:58, Haishan <hndxvon at 163.com> wrote: >> Hi, >> I try to add a backend (machine function) pass in LLVM 3.3 source code. >> In order to anal...

Hi Haishan, > int foo(int j) { > return ++j > 0; > } > int main() { > if (foo(((~0U)>>1))) > abort(); > exit(0) > } This test contains undefined behaviour, and you can never rely on the compiler doing anything predictable with that. Specifically, th...

...torture\execute\920612-1.c. gcc can handle it correctly. Moreover, when I compile this test using clang with optlevel O0 instead of O2. Its execution result is the same to gcc. That to say, for this test, clang with optlevel O2 execution result is different from O0. Is it reasonable? Thanks a lot. -Haishan At 2013-11-28 22:02:51,"Tim Northover" <t.p.northover at gmail.com> wrote: >Hi Haishan, > >> int foo(int j) { >> return ++j > 0; >> } >> int main() { >> if (foo(((~0U)>>1))) >> abort(); >> exit(0) &g...

> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Haishan > Subject: [LLVMdev] Question about Pre-RA-schedule in LLVM3.3 > My clang version is 3.3 and debug build. > //test.c > int a[6] = {1, 2, 3, 4, 5, 6} > int main() { >  a[0] = a[5]; >  a[1] = a[4]; >  a[2] = a[5]; > } > //end test.c > Then test.dump is generated by...

On Jan 3, 2014, at 1:52 PM, Andrew Trick <atrick at apple.com> wrote: > He really just wants to rerun LiveIntervals analysis, but LiveVariables is no longer available. Would it work just to clear all the intervals rerun LiveIntervals::computeVirtRegs after all the CFG transforms are complete? Yes, I should think so. /jakob -------------- next part -------------- An HTML attachment was

...AndEmitDAG function. PS: I once used IROrder which is a member of class SDNode as unchangeable information, but it's roughly corresponding information, so the map <Instruction*, vector<MachineInstr*> > often overlaps. Could someone help me with that? Thank you very much in advance. -Haishan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131212/0e32caec/attachment.html>

hi, I have few question about breaking anti-dependence of postRAScheduler in LLVM. when I use command line "clang -target arm -mcpu=cortex-a8 -O2 -integrated-as -c test.c -o test.o" and get objdump file as follows: ldrr1, [r0,#16]----(1 str r1, [r0,#32]----(2 ldr r1, [r0,#12]----(3 str r1, [r0,#36]----(4 ldr r1, [r0,#08]----(5 str r1, [r0,#40]----(6 However, I expect that instruction