search for: gsis

Wei, Quick question: Am I reading the code correctly, that even with per-device interrupt remap tables, that GSIs are accounted to the intremap table of the corresponding IOAPIC, presumably because the IOMMU sees interrupts generated as GSIs as coming from the IOAPIC? In that case, then we need all devices sharing the same IOAPIC must not have any vector collisions. Is that correct? -George ______________...

PV on HVM guests map GSIs into event channels; at restore time the event channels are resumed by restore_pirqs. Device drivers might try to register the same GSI again through ACPI at restore time, but the GSI has already been mapped and bound by restore_pirqs. This patch detects these situations and avoid mapping the same...

...ll VQs. > Again this doesn't scale: a single CPU has to handle > interrupts for all of them. > I think you need to find a way to get per-VQ interrupts. Yeah, AFAIK it's impossible to distribute works to different CPUs with only one irq without MSI-X kind mechanism. Assign multiple gsis to one device, obviously it's consumptive and not scalable. Any ideas? Thx. > >> -- >> 1.7.9.5 >> > > . >

...ll VQs. > Again this doesn't scale: a single CPU has to handle > interrupts for all of them. > I think you need to find a way to get per-VQ interrupts. Yeah, AFAIK it's impossible to distribute works to different CPUs with only one irq without MSI-X kind mechanism. Assign multiple gsis to one device, obviously it's consumptive and not scalable. Any ideas? Thx. > >> -- >> 1.7.9.5 >> > > . >

...oesn't scale: a single CPU has to handle > > interrupts for all of them. > > I think you need to find a way to get per-VQ interrupts. > > Yeah, AFAIK it's impossible to distribute works to different CPUs with > only one irq without MSI-X kind mechanism. Assign multiple gsis to one > device, obviously it's consumptive and not scalable. Why not? How many gsis are there on ARM? > Any ideas? Thx. > > > > >> -- > >> 1.7.9.5 > >> > > > > . > >

From: Li Liu <john.liuli at huawei.com> This irq handler will get the interrupt reason from a shared memory. And will be assigned only while irqfd enabled. Signed-off-by: Li Liu <john.liuli at huawei.com> --- drivers/virtio/virtio_mmio.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/virtio/virtio_mmio.c

From: Li Liu <john.liuli at huawei.com> This irq handler will get the interrupt reason from a shared memory. And will be assigned only while irqfd enabled. Signed-off-by: Li Liu <john.liuli at huawei.com> --- drivers/virtio/virtio_mmio.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/virtio/virtio_mmio.c

...int i = 0; + unsigned int i; /* Find the IOAPIC that manages this GSI. */ for (i = 0; i < nr_ioapics; i++) { @@ -955,7 +814,6 @@ void __init mp_register_ioapic ( * Build basic GSI lookup table to facilitate gsi->io_apic lookups * and to prevent reprogramming of IOAPIC pins (PCI GSIs). */ - mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; mp_ioapic_routing[idx].gsi_base = gsi_base; mp_ioapic_routing[idx].gsi_end = gsi_base + io_apic_get_redir_entries(idx); @@ -969,7 +827,7 @@ void __init mp_register_ioapic ( return; } -unsigned highest_gsi(void) +uns...

The following 5 patches are re-submissions of the vt-d patch. This set of patches has been tested against cs# 15080 and is now much more mature and tested against more environments than the original patch. Specifically, we have successfully tested the patch with following environements: - 32/64-bit Linux HVM guest - 32-bit Windows XP/Vista (64-bit should work but did not test) -

...ted Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> changeset: 23807:2297b90a6a7b user: Stefano Stabellini <stefano.stabellini@eu.citrix.com> date: Wed Aug 31 15:23:34 2011 +0100 xen: __hvm_pci_intx_assert should check for gsis remapped onto pirqs If the isa irq corresponding to a particular gsi is disabled while the gsi is enabled, __hvm_pci_intx_assert will always inject the gsi through the violapic, even if the gsi has been remapped onto a pirq. This patch makes sure that even in this case we injec...

Hi Ingo, Here''s the chunk of patches to add Xen Dom0 support (it''s probably worth creating a new xen/dom0 topic branch for it). A dom0 Xen domain is basically the same as a normal domU domain, but it has extra privileges to directly access hardware. There are two issues to deal with: - translating to and from the domain''s pseudo-physical addresses and real machine

...ueue_selector = ioport__read16(data); + break; + case VIRTIO_PCI_COMMON_Q_MSIX: + vec = vpci->vq_vector[vpci->queue_selector] = ioport__read16(data); + + if (vec == VIRTIO_MSI_NO_VECTOR) + break; + + gsi = irq__add_msix_route(vpci->kvm, &vpci->msix_table[vec].msg); + vpci->gsis[vpci->queue_selector] = gsi; + if (vdev->ops->notify_vq_gsi) + vdev->ops->notify_vq_gsi(vpci->kvm, vpci->dev, + vpci->queue_selector, gsi); + break; + case VIRTIO_PCI_COMMON_Q_SIZE: + val = ioport__read16(data); + break; + case VIRTIO_PCI_COMMON_Q_ENABLE: + val =...

...ueue_selector = ioport__read16(data); + break; + case VIRTIO_PCI_COMMON_Q_MSIX: + vec = vpci->vq_vector[vpci->queue_selector] = ioport__read16(data); + + if (vec == VIRTIO_MSI_NO_VECTOR) + break; + + gsi = irq__add_msix_route(vpci->kvm, &vpci->msix_table[vec].msg); + vpci->gsis[vpci->queue_selector] = gsi; + if (vdev->ops->notify_vq_gsi) + vdev->ops->notify_vq_gsi(vpci->kvm, vpci->dev, + vpci->queue_selector, gsi); + break; + case VIRTIO_PCI_COMMON_Q_SIZE: + val = ioport__read16(data); + break; + case VIRTIO_PCI_COMMON_Q_ENABLE: + val =...