search for: grx32bit

...  def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; The input to TwoAddress is: BB#0: derived from LLVM BB %0     Live Ins: %r2l         %vreg0<def> = COPY %r2l<kill>; GR32Bit:%vreg0         %vreg9<def,tied1> = NIFMux %vreg0<tied0>, 14, %cc<imp-def,dead>; GRX32Bit:%vreg9 GR32Bit:%vreg0         %vreg4<def,tied1> = NIFMux %vreg0<tied0>, 254, %cc<imp-def,dead>; GRX32Bit:%vreg4 GR32Bit:%vreg0         %vreg2<def> = COPY %vreg0<kill>; GR32Bit:%vreg2,%vreg0         %vreg3<def> = COPY %vreg9<kill>; GR32Bit:%vreg3 GRX32Bi...

...fPseudo<GRX32, GRX32>; > > The input to TwoAddress is: > > BB#0: derived from LLVM BB %0 > Live Ins: %r2l > %vreg0<def> = COPY %r2l<kill>; GR32Bit:%vreg0 > %vreg9<def,tied1> = NIFMux %vreg0<tied0>, 14, %cc<imp-def,dead>; GRX32Bit:%vreg9 GR32Bit:%vreg0 > %vreg4<def,tied1> = NIFMux %vreg0<tied0>, 254, %cc<imp-def,dead>; GRX32Bit:%vreg4 GR32Bit:%vreg0 > %vreg2<def> = COPY %vreg0<kill>; GR32Bit:%vreg2,%vreg0 > %vreg3<def> = COPY %vreg9<kill>; GR32Bit:%vr...

Hi, On SystemZ there are a set of "access registers" that can be copied in and out of 32-bit GPRs with special instructions. These instructions can only perform the copy using low 32-bit parts of the 64-bit GPRs. As reported and discussed at https://bugs.llvm.org/show_bug.cgi?id=44254, this is currently broken due to the fact that the default register class for 32-bit integers is

Hi, Using llvm-stress, I got a crash after Post-RA pseudo expansion, with machine verifier. A 128 bit register %vreg233:subreg_l32<def,read-undef> = LLCRMux %vreg119; GR128Bit:%vreg233 GRX32Bit:%vreg119 gets spilled: %vreg265:subreg_l32<def,read-undef> = LLCRMux %vreg119; GR128Bit:%vreg265 GRX32Bit:%vreg119 ST128 %vreg265, <fi#10>, 0, %noreg; mem:ST16[FixedStack10](align=8) GR128Bit:%vreg265 -> regalloc %R5L<def> = LLCRMux %R6L, %R4Q<imp-def> ST128 %R4Q&lt...