Displaying 2 results from an estimated 2 matches for "gr64regclass".
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gpr64regclass
2014 Feb 08
2
[LLVMdev] selecting ISD node - help
...ode.
> 2. Give your RDMSR node type MVT::Glue instead of MVT::Other
I tried doing what you said, and the DAG looks like how I think it supposed
to look like (attached the picture below).
if(Subtarget->is64Bit())
{
idReg = X86::RCX;
resultReg = MF.addLiveIn(X86::RAX, &X86::GR64RegClass);
}
else
{
idReg = X86::ECX;
resultReg = MF.addLiveIn(X86::EAX, &X86::GR32RegClass);
}
idRegValue = CurDAG->getRegister(idReg, resultType);
SDValue setIdNode = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
idRegValue, id, SDValue());
SDValue rdmsrNode...
2014 Feb 08
2
[LLVMdev] selecting ISD node - help
Hey, I wanted to add an intrinsics to read MSRs.
So I added the intrinsics and lowered it to a new ISD node I created
ISD::RDMSR, its first operand is the MSR id.
I added a case in X86DAGToDAGISel::Select for ISD::RDMSR.
Now I know rdmsr works like so:
mov r/ecx, <id>
rdmsr
r/eax holds the lower 32/64 bit
>From what I understood this needs a Token Factor node, nodes which are