Displaying 9 results from an estimated 9 matches for "gpr64regclass".
2012 Sep 05
5
[LLVMdev] 64 bit special purpose registers
Micah,
Do you mean we should make GPR64 available to register allocator by calling
addRegisterClass?
addRegisterClass(MVT::i64, &GPR64RegClass)
If we add register class GPR64, type legalization will stop expanding i64
operations because i64 is now a legal type.
Then we will probably have to write lots of code to custom-lower
unsupported 64-bit operations during legalization. Note that mips32/16
lacks support for most of the basic 64-bit...
2012 Sep 06
0
[LLVMdev] 64 bit special purpose registers
Hi Akira, Micah,
On 05/09/2012 21:44, Akira Hatanaka wrote:
> Micah,
>
> Do you mean we should make GPR64 available to register allocator by
> calling addRegisterClass?
>
> addRegisterClass(MVT::i64, &GPR64RegClass)
I have a related question to this thread. Does the RA use target
lowering information?
Because if it doesn't, you don't need to register your i64 reg class.
Ivan
>
> If we add register class GPR64, type legalization will stop expanding
> i64 operations because i64 is now a le...
2012 Sep 05
0
[LLVMdev] 64 bit special purpose registers
...om]
Sent: Wednesday, September 05, 2012 12:44 PM
To: Villmow, Micah
Cc: reed kotler; llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] 64 bit special purpose registers
Micah,
Do you mean we should make GPR64 available to register allocator by calling addRegisterClass?
addRegisterClass(MVT::i64, &GPR64RegClass)
If we add register class GPR64, type legalization will stop expanding i64 operations because i64 is now a legal type.
[Villmow, Micah] You'll have to set everything that you don't support to 'Expand' and everything you do support into 'Legal'.
Then we will probably have t...
2012 Sep 07
1
[LLVMdev] 64 bit special purpose registers
...n Llopard <ivanllopard at gmail.com> wrote:
> Hi Akira, Micah,
>
>
> On 05/09/2012 21:44, Akira Hatanaka wrote:
>
> Micah,
>
> Do you mean we should make GPR64 available to register allocator by
> calling addRegisterClass?
>
> addRegisterClass(MVT::i64, &GPR64RegClass)
>
>
> I have a related question to this thread. Does the RA use target lowering
> information?
> Because if it doesn't, you don't need to register your i64 reg class.
>
> Ivan
>
>
>
> If we add register class GPR64, type legalization will stop expanding i64...
2012 Sep 06
3
[LLVMdev] 64 bit special purpose registers
...6/2012 05:06 AM, Ivan Llopard wrote:
> Hi Akira, Micah,
>
> On 05/09/2012 21:44, Akira Hatanaka wrote:
>> Micah,
>>
>> Do you mean we should make GPR64 available to register allocator by
>> calling addRegisterClass?
>>
>> addRegisterClass(MVT::i64, &GPR64RegClass)
>
> I have a related question to this thread. Does the RA use target
> lowering information?
> Because if it doesn't, you don't need to register your i64 reg class.
>
> Ivan
>
>>
>> If we add register class GPR64, type legalization will stop expanding
>...
2012 Sep 06
0
[LLVMdev] 64 bit special purpose registers
...t;
> On 09/06/2012 05:06 AM, Ivan Llopard wrote:
>
> Hi Akira, Micah,
>
> On 05/09/2012 21:44, Akira Hatanaka wrote:
>
> Micah,
>
> Do you mean we should make GPR64 available to register allocator by calling
> addRegisterClass?
>
> addRegisterClass(MVT::i64, &GPR64RegClass)
>
>
> I have a related question to this thread. Does the RA use target lowering
> information?
> Because if it doesn't, you don't need to register your i64 reg class.
>
> Ivan
>
>
> If we add register class GPR64, type legalization will stop expanding i64
>...
2012 Sep 07
1
[LLVMdev] 64 bit special purpose registers
...;
> > Hi Akira, Micah,
> >
> > On 05/09/2012 21:44, Akira Hatanaka wrote:
> >
> > Micah,
> >
> > Do you mean we should make GPR64 available to register allocator by
> calling
> > addRegisterClass?
> >
> > addRegisterClass(MVT::i64, &GPR64RegClass)
> >
> >
> > I have a related question to this thread. Does the RA use target lowering
> > information?
> > Because if it doesn't, you don't need to register your i64 reg class.
> >
> > Ivan
> >
> >
> > If we add register class GPR...
2012 Aug 07
0
[LLVMdev] 64 bit special purpose registers
This can be done by declaring a register class with these registers and only using that register class as an operand in the instructions where it is legal.
You then set as sub registers what you want to represent as the hi and lo registers for those 64bit registers.
So something like this:
def lo_comp : SubRegIndex;
def hi_comp : SubRegIndex;
def R1 : Register<1>;
def R2 :
2012 Aug 06
2
[LLVMdev] 64 bit special purpose registers
On Mips 32 there is traditionally a 64 bit HI/LO register for the result
of multiplying two 64 bit numbers.
There are corresponding instructions to load the LO and HI parts into
individual 32 registers.
On Mips with the DSP ASE (an application specific extension), there are
actual 4 such pairs of
registers.
Is there a way to have special purpose 64 bit registers without actually
having to