search for: gr32_

...t is the ValueType needed for? Isn't the register id itself an indication of the ValueType it represents? Where I'm at I don't have access to a ValueType. I understand that a physical register can live in multiple classes (cf. X86RegisterInfo.td where EAX and others are in GR32 and GR32_, though the comment says GR32_ is only for 32 bit mode, so it's not _really_ the case that it's in multiple classes). Does ValueType have something to do with that? In the same file, the VR64 register class has the following definition: def VR64 : RegisterClass<"X86", [v8i...

...his simply functionality that >>> has not been written yet? The existing backends seem to have only >>> one >>> register class per machine value type. >> >> The x86 backend has an example of a partial solution. The GR32 >> register class has a subset, GR32_, which is the registers in GR32 >> that support 8-bit subregs. Instructions that reference 8-bit >> subregs >> are emitted with a copy (MOV32to32_) to put the value in a virtual >> register of the needed class. This copy may then optimized away >> by subsequent pas...

...misusing register classes, or is this simply functionality that >> has not been written yet? The existing backends seem to have only one >> register class per machine value type. > > The x86 backend has an example of a partial solution. The GR32 > register class has a subset, GR32_, which is the registers in GR32 > that support 8-bit subregs. Instructions that reference 8-bit subregs > are emitted with a copy (MOV32to32_) to put the value in a virtual > register of the needed class. This copy may then optimized away > by subsequent passes. I missed this before...

How do I get the TargetRegisterClass for a physical register? SSARegMap::getRegClass only works for virtual registers. -Dave

Take a look at getPhysicalRegisterRegClass( const MRegisterInfo *MRI, MVT::ValueType VT, unsigned reg) in ScheduleDAG.cpp. -- Christopher Lamb On Jun 18, 2007, at 4:52 PM, David A. Greene wrote: > How do I get the TargetRegisterClass for a physical register? > SSARegMap::getRegClass only works for virtual registers. > >

...> > Am I misusing register classes, or is this simply functionality that > has > not been written yet? The existing backends seem to have only one > register class per machine value type. The x86 backend has an example of a partial solution. The GR32 register class has a subset, GR32_, which is the registers in GR32 that support 8-bit subregs. Instructions that reference 8-bit subregs are emitted with a copy (MOV32to32_) to put the value in a virtual register of the needed class. This copy may then optimized away by subsequent passes. Right now the x86 target code has to expl...

On Mon, 2 Oct 2006, Roman Levenstein wrote: >>> Wouldn't it be possible and even more clean to have just one >>> description like (I use a pseudo-description here): >>> >>> def MOVrr : I<0x88, MRMDestReg, (ops (GR8|GR16|GR32) :$dst, >>> (i8mem|i16mem|i32mem):$src), >>> "mov{b} {$src, $dst|$dst, $src}", []>,

...I have to call some other pass after LowerSelect to recompute some properties and to bring the code again into the correct form? Any ideas? BTW, which pass(es) does transformation of PHIs into copies during code selection? 2) In the X86 target, I've seen the special register classes GR16_ and GR32_, which are subsclasses of GR16 and GR32. These two classes are used just in a few places inside the instructions definition file. There they are only used to define the fact that normal regs from GR32 can be moved into GR32_ regs. This is not quite obvious for me why this classes are introduced at...

Hi Chris, Thanks a lot for your answer! Chris Lattner wrote: >> 1. Why does X86 instruction set description provide different >> descriptions for the same instructions, which differ only in the size >> of operands? >> E.g. >> >> def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src), >> "mov{b} {$src, $dst|$dst, $src}",

Hi, I am writing a backend for the Blackfin processor from Analog Devices. I just started so I still have a lot to learn about the code generator. So far, I can compile test/CodeGen/Generic/BasicInstrs.ll correctly, but that is about it. The Blackfin 32-bit registers divide naturally into several classes. I have modelled these register classes without knowing anything about what the code