Displaying 8 results from an estimated 8 matches for "gr16_".
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gr16
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
...8bit : PatLeaf<(i32 0)>;
def : SubRegSet<0, [AX, CX, DX, BX, SP, BP, SI, DI,
R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
[AL, CL, DL, BL, SPL, BPL, SIL, DIL,
R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
class GR16_ ..... {
let SubRegClassList = [GR8];
}
Refer to below functions in ScheduleDAGEmit.cpp:
-----------------------------------------------
static const TargetRegisterClass*
getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx)
{
// Pick the register class of the subregister...
2008 Oct 15
0
[LLVMdev] INSERT_SUBREG node.
...;
>
> def : SubRegSet<0, [AX, CX, DX, BX, SP, BP, SI, DI,
> R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
> [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
> R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
>
>
> class GR16_ ..... {
> let SubRegClassList = [GR8];
> }
Right. Subreg index starts from 1. This ought to be fixed but it's not
(yet).
>
>
> The getSubRegisterRegClass uses SubIdx - 1;
>
> so INSERT_SUBREG (IMPLICIT_DEF, AL, 0) will not work, because
> getSubRegisterRegClas...
2008 Oct 14
0
[LLVMdev] INSERT_SUBREG node.
You need to specify sub-register == super-register, idx relationship.
See X86RegisterInfo.td:
def x86_subreg_8bit : PatLeaf<(i32 1)>;
def x86_subreg_16bit : PatLeaf<(i32 2)>;
def x86_subreg_32bit : PatLeaf<(i32 3)>;
def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
[AL, CL,
2008 Oct 13
2
[LLVMdev] INSERT_SUBREG node.
On Thu, 2008-10-02 at 11:19 -0700, Evan Cheng wrote:
>
> On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote:
>
> > What’s the value produced by an INSERT_SUBREG node? Is it a chain?
>
>
> No, insert_subreg returns a value:
>
>
> v1 = insert_subreg v2, v3, idx
>
>
> v1 and v2 will have the same type, e.g. i16, and v3 must have a
>
2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
...;0, [AX, CX, DX, BX, SP, BP, SI, DI,
> > R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
> > [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
> > R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
> >
> >
> > class GR16_ ..... {
> > let SubRegClassList = [GR8];
> > }
>
> Right. Subreg index starts from 1. This ought to be fixed but it's not
> (yet).
>
> >
> >
> > The getSubRegisterRegClass uses SubIdx - 1;
> >
> > so INSERT_SUBREG (IMPLICIT_DEF, AL,...
2006 Oct 02
0
[LLVMdev] Instruction descriptions question
On Mon, 2 Oct 2006, Roman Levenstein wrote:
>>> Wouldn't it be possible and even more clean to have just one
>>> description like (I use a pseudo-description here):
>>>
>>> def MOVrr : I<0x88, MRMDestReg, (ops (GR8|GR16|GR32) :$dst,
>>> (i8mem|i16mem|i32mem):$src),
>>> "mov{b} {$src, $dst|$dst, $src}", []>,
2006 Oct 03
2
[LLVMdev] Questions about instruction selection and instruction definitions
...s? May be I have to call some
other pass after LowerSelect to recompute some properties and to bring
the code again into the correct form? Any ideas?
BTW, which pass(es) does transformation of PHIs into copies during code
selection?
2) In the X86 target, I've seen the special register classes GR16_ and
GR32_, which are subsclasses of GR16 and GR32. These two classes are
used just in a few places inside the instructions definition file.
There they are only used to define the fact that normal regs from GR32
can be moved into GR32_ regs. This is not quite obvious for me why this
classes are intr...
2006 Oct 02
2
[LLVMdev] Instruction descriptions question
Hi Chris,
Thanks a lot for your answer!
Chris Lattner wrote:
>> 1. Why does X86 instruction set description provide different
>> descriptions for the same instructions, which differ only in the
size
>> of operands?
>> E.g.
>>
>> def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src),
>> "mov{b} {$src, $dst|$dst, $src}",