search for: gpr8

...this way: <stripped version of my code)> // 8 bit regs def R0 : Register<"r0">, DwarfRegNum<[0]>; def R1 : Register<"r1">, DwarfRegNum<[1]>; // reg pairs def R1R0 : RegisterWithSubRegs<"r0", [R0, R1]>, DwarfRegNum<[0]>; def GPR8 : RegisterClass<"TEST", [i8], 8, [R0, R1]>; def WDREGS : RegisterClass<"TEST", [i16], 16, [R1R0]> { let SubRegClassList = [GPR8, GPR8]; } This way i could work with register pairs easily, for example storing i16 data inside the WDREGS class or i32 inside 2 WDRE...

Hello, while testing trivial functions in my backend i noticed a suboptimal way of assigning regs that had the following pattern, consider the following function: typedef unsigned short t; t foo(t a, t b) { t a4 = b^a^18; return a4; } Argument "a" is passed in R15:R14 and argument "b" is passed in R13:R12, the return value is stored in R15:R14. Producing the

...)> > > // 8 bit regs > def R0 : Register<"r0">, DwarfRegNum<[0]>; > def R1 : Register<"r1">, DwarfRegNum<[1]>; > > // reg pairs > def R1R0 : RegisterWithSubRegs<"r0", [R0, R1]>, DwarfRegNum<[0]>; > > def GPR8 : RegisterClass<"TEST", [i8], 8, [R0, R1]>; > def WDREGS : RegisterClass<"TEST", [i16], 16, [R1R0]> > { > let SubRegClassList = [GPR8, GPR8]; > } > > This way i could work with register pairs easily, for example storing i16 > data inside the...

...r and -immediate, but for now if I could just get LLVM to use SUB8ri in the most straightforward case that would work for me. Thanks, Joshua // SUB8ri definition let Constraints = "$src = $dst" in def SUB8ri : Instruction { let Namespace = "AVR"; dag OutOperandList = (outs GPR8:$dst); dag InOperandList = (ins GPR8:$src, i8imm:$src2); let AsmString = "SUB\t{$dst, $src2}"; let Pattern = [(set GPR8:$dst, (opnode GPR8:$src, imm:$src2))]; } Joshua Nedrud Master of Science, Biomedical Engineering

Hello > and as the return value. Is this a missed optimization from LLVM or did i > miss something out? > Changing the register allocation order didnt work. What are the patterns for xor / mov ? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

Indeed, i've marked it as commutable: let isCommutable = 1, isTwoAddress = 1 in def XORRdRr : FRdRr<0b0010, 0b01, (outs GPR8:$dst), (ins GPR8:$src1, GPR8:$src2), "xor\t$dst, $src2", [(set GPR8:$dst, (xor GPR8:$src1, GPR8:$src2))]>; -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llv...

...fact you said that the subregister class is larger than the superregister class. As far as i understood or what i tried to do with my code is to define a register pair composed of two 8 bit registers the way i described in my previous message. So R1R0 in WDREGS is directly mapped into R0 and R1 of GPR8. Meaning that 2 GPR8 = 1 WDREG. Also, R1R0 is the superreg of R1 and R0? Incase i wasnt clear enough i'll expose a simple example using the common known x86 arch. AX is composed by AL and AH (AX and AH are subregs of AX), now assume x86 can only add regs of 8 bits, so if a i16 number is stored...

...mullohi returns two results, which is the problem. I am not sure how to match against multiple results. The only other nodes to return two operands are umullohi, udivrem, and sdivrem. There are no examples of these in TableGen in tree. The closest I can get is this: set (R1, R0, (umullohi GPR8:$lhs, GPR8:$rhs)) Which fails: Assertion failed: (Ops.size() >= NumSrcResults && "Didn't provide enough results"), function EmitResultCode, file /Users/dylanmckay/projects/llvm/avr-llvm/utils/TableGen/DAGISelMatcherGen.cpp, line 989. 0 libLLVMSupport.dylib 0...

...23R22 in reg%16385 Function Live Outs: %R25R24 BB#0: derived from LLVM BB %entry Live Ins: %R25R24 %R23R22 %reg16385<def> = COPY %R23R22; WDREGS:%reg16385 // COPY B %reg16384<def> = COPY %R25R24; WDREGS:%reg16384 // COPY A %reg16387<def> = COPY %reg16384:ssub_0; GPR8:%reg16387 WDREGS:%reg16384 // EXTRACT LO BYTE OF A %reg16388<def> = COPY %reg16385:ssub_0; GPR8:%reg16388 WDREGS:%reg16385 // EXTRACT LO BYTE OF B %reg16389<def> = COPY %reg16384:ssub_1; GPR8:%reg16389 WDREGS:%reg16384 // EXTRACT HI BYTE OF A %reg16390<def> = COPY %reg...

Hello LLVMDevs, I am looking for an example for how to lower LLVM IR to mulsu kind of instruction. I found that AVR back end have such instruction but AVRInstrInfo.td does not define any DAG pattern for which this instruction gets emitted. def MULSURdRr : FMUL2RdRr<1, (outs), (ins GPR8:$lhs, GPR8:$rhs), "mulsu\t$lhs, $rhs", []>, Requires<[SupportsMultiplication]>; Also simple grep around related words does not show any other information. Can some one explain me how this kind of instruction should be lowered ? Sincerely, Vivek -------------- next part -------...

...ple for how to lower LLVM IR to mulsu kind of >> instruction. I found that AVR back end have such instruction but >> AVRInstrInfo.td does not define any DAG pattern for which this >> instruction gets emitted. >> def MULSURdRr : FMUL2RdRr<1, >> (outs), >> (ins GPR8:$lhs, GPR8:$rhs), >> "mulsu\t$lhs, $rhs", >> []>, >> Requires<[SupportsMultiplication]>; >> Also simple grep around related words does not show any other >> information. >> >> Can some one explain me how this kind of instruction should b...

...to describe them in InstrInfo.td as seperate instructions. Note that R27R26 is a pointer register defined in AVRRegisterInfo.td, and 'X' is an alias for this. let Uses = [R27R26], canFoldAsLoad = 1, isReMaterializable = 1 in def LDRdX : FSTLDPtrReg<0b0, (outs GPR8:$reg), (ins), "ld\t$reg, X", [(set GPR8:$reg, (load R27R26))]>; def LDRdY : FSTLDPtrReg<0b0, // ... When I do this, however, I get errors that the pointer register is an invalid operand type. Another...

TableGen, as a DSL language, is made up of records. Every def corresponds to a record. For example, TableGen has a class Register, and your backend will define records by def GPR8 : Register<...>. You are correct in saying that the record definition is one of the SDNode values. These correspond 1:1 to llvm::ISD::NodeType <http://llvm.org/docs/doxygen/html/namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110> . (DEF a, b) corresponds to --------- a...

...h is the problem. I am not sure how to > match against multiple results. The only other nodes to return two operands > are umullohi, udivrem, and sdivrem. There are no examples of these in > TableGen in tree. > > The closest I can get is this: > > set (R1, R0, (umullohi GPR8:$lhs, GPR8:$rhs)) > > > As far as I know, you cannot define a tablegen pattern with multiple > results, and need to use C++ matching. I’m kind of surprised there are > defined td nodes for these. > > -Matt > -------------- next part -------------- An HTML attachment was scru...

On Fri, Jan 29, 2016 at 11:39 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > > On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> > wrote: > >> Try visualising the DAG like this. >> >> ``` >> ---- GPR:$rA >> / >> set GPR:$rd ---- add >>

...vm.org.cn> wrote: >>> >>> Hi Daniel, >>> >>> Thanks for your response! >>> >>> >>> 在 2017年12月19日 18:53, Daniel Sanders 写道: >>>> >>>> Hi Leslie, >>>> >>>> There should be a definition of GPR8RegClassID in >>>> $build_dir/lib/Target/AVR/AVRGenRegisterInfo.inc which should be included by >>>> AVRRegisterInfo.h. AArch64 includes its AArch64RegisterInfo.h in >>>> AArch64InstructionSelector.cpp but it seems that ARM gets it indirectly when >>>>...

I can't get it to work with pattern matching. My operand is defined like so: def LDSTPtrReg : Operand<i16> { let MIOperandInfo = (ops PTRREGS); let EncoderMethod = "encodeLDSTPtrReg"; } I am able to use it in the place of PTRREGS in the definition of the LD instruction, but if I use it in an instruction matching pattern, compilation fails with the error "Unknown

Thanks. I saw the header comments but it wasn’t clear to me what the difference between those concepts is? My slightly vague understanding is IsDef means that the register specified by this operand is set by the machine instruction. So I understand that to mean the MO will override that register? Also things like early clobber, perhaps there is another document that clarifies some of these

On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> wrote: > Try visualising the DAG like this. > > ``` > ---- GPR:$rA > / > set GPR:$rd ---- add > \ > ---- GPR:$rB > ``` > > Each instruction forms a DAG with its operands being subnodes. > >