search for: gp10b_mmu_new

Displaying 8 results from an estimated 8 matches for "gp10b_mmu_new".

Did you mean: gf100_mmu_new
2017 Nov 10
2
GP10B regression
Hello everyone, it seems that GP10B support has regressed recently. With linux-next, I need to modify device/base.c to set .mmu = gp10b_mmu_new for GP10B (makes sense - I guess this was left as gf100_mmu_new as a typo) to probe. After that, running a trivial testcase (running a NOP method in 3D class) fails with [ 110.084649] nouveau 17000000.gpu: fifo: read fault at 0000011000 engine 06 [HOST0] client 06 [GPC0/L1_2] reas| on 02 [PTE...
2017 Nov 11
0
GP10B regression
...t is d7722134b825 drm/nouveau: switch over to new memory and vmm interfaces Even with the first one some patches/hacks are needed: - in mmu/gp10b.c, in the constructor we need to select the GM200 path - the GP100 path seems to not to work - as mentioned in the first mail, we need to set .mmu = gp10b_mmu_new, - and in nouveau_mem_memory_target we need to return NVKM_MEM_TARGET_NCOH instead of NVKM_MEM_TARGET_HOST. Cheers, Mikko On 11/10/2017 11:27 PM, Mikko Perttunen wrote: > Hello everyone, > > it seems that GP10B support has regressed recently. With linux-next, I > need to modify de...
2017 Nov 21
2
GP10B regression
...100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2369,7 +2369,7 @@ nv13b_chipset = { .imem = gk20a_instmem_new, .ltc = gp100_ltc_new, .mc = gp10b_mc_new, - .mmu = gf100_mmu_new, + .mmu = gp10b_mmu_new, .secboot = gp10b_secboot_new, .pmu = gm20b_pmu_new, .timer = gk20a_timer_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c index 3dcc6bddb32f..470a4fadc165 100644 --- a/drivers/gpu/drm/nouveau/nvkm/...
2019 Sep 16
0
[PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation
.../device/base.c > > @@ -2380,7 +2380,7 @@ nv13b_chipset = { > > .fuse = gm107_fuse_new, > > .ibus = gp10b_ibus_new, > > .imem = gk20a_instmem_new, > > - .ltc = gp102_ltc_new, > > + .ltc = gp10b_ltc_new, > > .mc = gp10b_mc_new, > > .mmu = gp10b_mmu_new, > > .secboot = gp10b_secboot_new, > > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild > > index 2b6d36ea7067..728d75010847 100644 > > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild > > +++ b/drivers...
2019 Sep 16
1
[PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation
...+2380,7 @@ nv13b_chipset = { > > > .fuse = gm107_fuse_new, > > > .ibus = gp10b_ibus_new, > > > .imem = gk20a_instmem_new, > > > - .ltc = gp102_ltc_new, > > > + .ltc = gp10b_ltc_new, > > > .mc = gp10b_mc_new, > > > .mmu = gp10b_mmu_new, > > > .secboot = gp10b_secboot_new, > > > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild > > > index 2b6d36ea7067..728d75010847 100644 > > > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild &gt...
2019 Sep 16
15
[PATCH 00/11] drm/nouveau: Enable GP10B by default
From: Thierry Reding <treding at nvidia.com> Hi, the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why exactly is not clear, but there are slight differences between the SKUs that were tested. It turns out that the biggest issue is that on some devices (e.g. the one that I have), pulsing the GPU reset twice as is done in the current code (once as part of the power-ungate
2019 Nov 02
13
[PATCH v2 0/9] drm/nouveau: Various fixes for GP10B
From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the
2019 Dec 09
11
[PATCH v3 0/9] drm/nouveau: Various fixes for GP10B
From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the