search for: gf100_mmu_new

...b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 7bdc7a5ae723..a6221b0996bf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2166,6 +2166,7 @@ nv130_chipset = { .ltc = gp100_ltc_new, .mc = gp100_mc_new, .mmu = gf100_mmu_new, + .therm = gp100_therm_new, .secboot = gm200_secboot_new, .pci = gp100_pci_new, .pmu = gp100_pmu_new, @@ -2200,6 +2201,7 @@ nv132_chipset = { .ltc = gp100_ltc_new, .mc = gp100_mc_new, .mmu = gf100_mmu_new, + .therm = gp100_therm_new, .secboot = gp102_secboot_new, .pci = gp100_pci_n...

...b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index e096a5d9c292..28fd4fa98635 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2169,6 +2169,7 @@ nv130_chipset = { .ltc = gp100_ltc_new, .mc = gp100_mc_new, .mmu = gf100_mmu_new, + .therm = gp100_therm_new, .secboot = gm200_secboot_new, .pci = gp100_pci_new, .pmu = gp100_pmu_new, @@ -2203,6 +2204,7 @@ nv132_chipset = { .ltc = gp100_ltc_new, .mc = gp100_mc_new, .mmu = gf100_mmu_new, + .therm = gp100_therm_new, .secboot = gp102_secboot_new, .pci = gp100_pci_n...

overall it is for the most part the same as my older version. I cleaned up some copyright things, so that it is more like the others. Also I moved the print about the max speed supported into preinit and did some other minor cleanups in the 3rd commit. Happy testing (and performance for prime offloading setups) Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement

Hello everyone, it seems that GP10B support has regressed recently. With linux-next, I need to modify device/base.c to set .mmu = gp10b_mmu_new for GP10B (makes sense - I guess this was left as gf100_mmu_new as a typo) to probe. After that, running a trivial testcase (running a NOP method in 3D class) fails with [ 110.084649] nouveau 17000000.gpu: fifo: read fault at 0000011000 engine 06 [HOST0] client 06 [GPC0/L1_2] reas| on 02 [PTE] on channel 1 [00f206a000 nouveau_noop_te[2413]]...

this patch series implements PCIe speed changes for Tesla and newer. The Kepler and Fermi bits are tested on my cards at home. Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement generic code for PCIe speed change pci: implement pcie speed change for tesla pci: implement pcie speed change on Fermi pci: implement PCIe speed change for kepler+ bios/perf:

...00_bar_new, + .bios = nvkm_bios_new, + .bus = gf100_bus_new, + .devinit = gm200_devinit_new, + .fb = gp104_fb_new, + .fuse = gm107_fuse_new, + .gpio = gk104_gpio_new, + .i2c = gm200_i2c_new, + .ibus = gm200_ibus_new, + .imem = nv50_instmem_new, + .ltc = gp100_ltc_new, + .mc = gp100_mc_new, + .mmu = gf100_mmu_new, + .pci = gp100_pci_new, + .timer = gk20a_timer_new, + .top = gk104_top_new, + .ce[0] = gp104_ce_new, + .ce[1] = gp104_ce_new, + .ce[2] = gp104_ce_new, + .ce[3] = gp104_ce_new, + .disp = gp104_disp_new, + .dma = gf119_dma_new, + .fifo = gp100_fifo_new, +}; + static int nvkm_device_event_ctor(stru...

overall the same as the old stuff, but with better namings and tirivialy improved code here and there Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement generic code for PCIe speed change pci: implement pcie speed change for tesla pci: implement pcie speed change on Fermi pci: implement PCIe speed change for kepler+ bios/perf: parse the pci speed from the

....devinit = gm200_devinit_new, > .fb = gp102_fb_new, > .fuse = gm107_fuse_new, > .gpio = gk104_gpio_new, > .i2c = gm200_i2c_new, > .ibus = gm200_ibus_new, > .imem = nv50_instmem_new, > .ltc = gp100_ltc_new, > .mc = gp100_mc_new, > .mmu = gf100_mmu_new, > .pci = gp100_pci_new, > .pmu = gp102_pmu_new, > .timer = gk20a_timer_new, > .top = gk104_top_new, > .ce[0] = gp102_ce_new, > .ce[1] = gp102_ce_new, > .ce[2] = gp102_ce_new, > .ce[3] = gp102_ce_new, > .disp = gp102_disp_new, >...

...00_bar_new, + .bios = nvkm_bios_new, + .bus = gf100_bus_new, + .devinit = gm200_devinit_new, + .fb = gp104_fb_new, + .fuse = gm107_fuse_new, + .gpio = gk104_gpio_new, + .i2c = gm200_i2c_new, + .ibus = gm200_ibus_new, + .imem = nv50_instmem_new, + .ltc = gp100_ltc_new, + .mc = gp100_mc_new, + .mmu = gf100_mmu_new, + .pci = gp100_pci_new, + .timer = gk20a_timer_new, + .top = gk104_top_new, + .ce[0] = gp104_ce_new, + .ce[1] = gp104_ce_new, + .ce[2] = gp104_ce_new, + .ce[3] = gp104_ce_new, + .disp = gp104_disp_new, + .dma = gf119_dma_new, + .fifo = gp100_fifo_new, +}; + static int nvkm_device_event_ctor(stru...

...0_bus_new, > + .devinit = gm200_devinit_new, > + .fb = gp104_fb_new, > + .fuse = gm107_fuse_new, > + .gpio = gk104_gpio_new, > + .i2c = gm200_i2c_new, > + .ibus = gm200_ibus_new, > + .imem = nv50_instmem_new, > + .ltc = gp100_ltc_new, > + .mc = gp100_mc_new, > + .mmu = gf100_mmu_new, > + .pci = gp100_pci_new, > + .timer = gk20a_timer_new, > + .top = gk104_top_new, > + .ce[0] = gp104_ce_new, > + .ce[1] = gp104_ce_new, > + .ce[2] = gp104_ce_new, > + .ce[3] = gp104_ce_new, > + .disp = gp104_disp_new, > + .dma = gf119_dma_new, > + .fifo = gp100_fifo_n...

....fb = gp104_fb_new, > + .fuse = gm107_fuse_new, > + .gpio = gk104_gpio_new, > + .i2c = gm200_i2c_new, > + .ibus = gm200_ibus_new, > + .imem = nv50_instmem_new, > + .ltc = gp100_ltc_new, > + .mc = gp100_mc_new, > + .mmu = gf100_mmu_new, > + .pci = gp100_pci_new, > + .timer = gk20a_timer_new, > + .top = gk104_top_new, > + .ce[0] = gp104_ce_new, > + .ce[1] = gp104_ce_new, > + .ce[2] = gp104_ce_new, > + .ce[3] = gp104_ce_new, > + .disp = gp104_disp_new, > +...

...00_bar_new, + .bios = nvkm_bios_new, + .bus = gf100_bus_new, + .devinit = gm200_devinit_new, + .fb = gp102_fb_new, + .fuse = gm107_fuse_new, + .gpio = gk104_gpio_new, + .i2c = gm200_i2c_new, + .ibus = gm200_ibus_new, + .imem = nv50_instmem_new, + .ltc = gp100_ltc_new, + .mc = gp100_mc_new, + .mmu = gf100_mmu_new, + .pci = gp100_pci_new, + .pmu = gp102_pmu_new, + .timer = gk20a_timer_new, + .top = gk104_top_new, + .ce[0] = gp102_ce_new, + .ce[1] = gp102_ce_new, + .ce[2] = gp102_ce_new, + .ce[3] = gp102_ce_new, + .disp = gp102_disp_new, + .dma = gf119_dma_new, + .fifo = gp100_fifo_new, +}; + +static const st...

...s, Mikko On 11/10/2017 11:27 PM, Mikko Perttunen wrote: > Hello everyone, > > it seems that GP10B support has regressed recently. With linux-next, I > need to modify device/base.c to set > >     .mmu = gp10b_mmu_new > > for GP10B (makes sense - I guess this was left as gf100_mmu_new as a > typo) to probe. After that, running a trivial testcase (running a NOP > method in 3D class) fails with > > [  110.084649] nouveau 17000000.gpu: fifo: read fault at 0000011000 > engine 06 [HOST0] client 06 [GPC0/L1_2] reas| > on 02 [PTE] on channel 1 [00f206a000 nouveau_...

...ex e14643615698..00eeaaffeae5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2369,7 +2369,7 @@ nv13b_chipset = { .imem = gk20a_instmem_new, .ltc = gp100_ltc_new, .mc = gp10b_mc_new, - .mmu = gf100_mmu_new, + .mmu = gp10b_mmu_new, .secboot = gp10b_secboot_new, .pmu = gm20b_pmu_new, .timer = gk20a_timer_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c index 3dcc6bddb32f..470a4fadc165 100644 --- a...

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot:

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,