search for: gm20b_clk

This series adds support for GM20B PLL's Maxwell features, namely glitchless switch and (more importantly) DFS support. DFS lets the PLL lower its output speed according to input current variations, making the clock more stable and allowing it to run safely at lower voltage. All GM20B additions are done in the last patch, which consequently ends up being considerably big ; fortunately, it

When gk20a_clk_ctor() returns an error code, pointer "clk" should be released. It's the same when gm20b_clk_new() returns from elsewhere following this call. Signed-off-by: Dinghao Liu <dinghao.liu at zju.edu.cn> --- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c b/drivers/...

.../gm20b.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drm/nouveau/nvkm/subdev/clk/gm20b.c b/drm/nouveau/nvkm/subdev/clk/gm20b.c index 3089e4bc5e54..4ea89f71cd4f 100644 --- a/drm/nouveau/nvkm/subdev/clk/gm20b.c +++ b/drm/nouveau/nvkm/subdev/clk/gm20b.c @@ -946,11 +946,13 @@ gm20b_clk_init_fused_params(struct gm20b_clk *clk) { struct nvkm_subdev *subdev = &clk->base.base.subdev; u32 val; - u32 rev; + u32 rev = 0; +#if IS_ENABLED(CONFIG_ARCH_TEGRA) tegra_fuse_readl(FUSE_RESERVED_CALIB0, &val); rev = (val >> FUSE_RESERVED_CALIB0_FUSE_REV_SHIFT) &...

On Sat, 30 May 2020 at 19:42, Dinghao Liu <dinghao.liu at zju.edu.cn> wrote: > > When gk20a_clk_ctor() returns an error code, pointer "clk" > should be released. It's the same when gm20b_clk_new() > returns from elsewhere following this call. This shouldn't be necessary. If a subdev constructor fails, and returns a pointer, the core will call the destructor to clean things up. Ben. > > Signed-off-by: Dinghao Liu <dinghao.liu at zju.edu.cn> > --- > drivers/g...