search for: gk20a_clk

This series adds support for GM20B PLL's Maxwell features, namely glitchless switch and (more importantly) DFS support. DFS lets the PLL lower its output speed according to input current variations, making the clock more stable and allowing it to run safely at lower voltage. All GM20B additions are done in the last patch, which consequently ends up being considerably big ; fortunately, it

...name enable/disable functions clk/gk20a: fix VCO bit mask clk/gk20a: only compute n_lo if needed clk/gk20a: only restore divider to 1:1 if needed clk/gk20a: emit parent rate as debug message clk/gk20a: put mnp values into their own struct clk/gk20a: abstract pl_to_div clk/gk20a: split gk20a_clk_new() clk/gk20a: set lowest frequency during init() clk/gk20a: share reusable structures/functions clk/gm20b: add basic driver Vince Hsu (1): volt/gk20a: share reusable members & functions drm/nouveau/include/nvkm/subdev/clk.h | 1 + drm/nouveau/include/nvkm/subdev/volt.h | 1 +...

some chipset have working engine reclocking, but broken memory reclocking like Fermi. We should for now, add the functionality to allow partly reclocking for those. Allthough this doesn't give as much performance as one might wish, it is till noticeable and may improve performance enough to be noted. Karol Herbst (2): clk: seperate engine and memory reclock toggles clk: allow engine

....domains = { { nv_clk_src_crystal, 0xff }, { nv_clk_src_href , 0xff }, diff --git a/drm/nouveau/nvkm/subdev/clk/gk20a.c b/drm/nouveau/nvkm/subdev/clk/gk20a.c index 5f0ee24..8b64cc9 100644 --- a/drm/nouveau/nvkm/subdev/clk/gk20a.c +++ b/drm/nouveau/nvkm/subdev/clk/gk20a.c @@ -636,6 +636,7 @@ gk20a_clk = { .calc = gk20a_clk_calc, .prog = gk20a_clk_prog, .tidy = gk20a_clk_tidy, + .update = nv40_clk_update, .pstates = gk20a_pstates, .nr_pstates = ARRAY_SIZE(gk20a_pstates), .domains = { diff --git a/drm/nouveau/nvkm/subdev/clk/gm20b.c b/drm/nouveau/nvkm/subdev/clk/gm20b.c index 71b2bbb.....

This series addresses various issues inside the reclocking code: 1. after resume the set clocks are reset 2. reclocking not possible while GPU is suspended 3. nouveau always does full reclocks even if only a change of the voltage is required Some of the patches were part of the bigger reclocking series I sent months ago, some things have changed though. This is also preparation work of

We are slowly getting there! v4 of the series with some realy good improvements, so I am sure this is like 95% done and only needs some proper polishing and proper Reviews! I also added the NvVoltOffsetmV module parameter, so that a user is able to over and !under!-volt the GPU. Overvolting makes sense, when there are still some reclocking issues left, which might be solved by a higher voltage.