search for: gk20a_pll

This series adds support for GM20B PLL's Maxwell features, namely glitchless switch and (more importantly) DFS support. DFS lets the PLL lower its output speed according to input current variations, making the clock more stable and allowing it to run safely at lower voltage. All GM20B additions are done in the last patch, which consequently ends up being considerably big ; fortunately, it

...lowest speedo of Tegra X1. Ben, it would be super-duper great if you could take these in for 4.6. Not too big a deal if you cannot however. Alexandre Courbot (15): volt/gk20a: split constructor volt: add GM20B driver clk/gk20a: convert parameters to Khz clk/gk20a: reorganize variables in gk20a_pllg_calc_mnp() clk/gk20a: rename enable/disable functions clk/gk20a: fix VCO bit mask clk/gk20a: only compute n_lo if needed clk/gk20a: only restore divider to 1:1 if needed clk/gk20a: emit parent rate as debug message clk/gk20a: put mnp values into their own struct clk/gk20a: abstract p...