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...tal error of multiple definitions on destination register (Dest), from lib/CodeGen/LiveIntervalAnalysis.cpp. Certainly those addReg seems to be done wrongly. Any hint as to what must be the correct steps? Thanks. Girish. From: Jim Grosbach <grosbach at apple.com> >To: girish gulawani <girishvg at yahoo.com> >Cc: Johannes Birgmeier <e0902998 at student.tuwien.ac.at>; LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >Sent: Wednesday, 21 December 2011 11:30 PM >Subject: Re: [LLVMdev] Stop MachineCSE on certain instructions > > >Ah, OK. I think I unde...

...s a CSE case. Please note this is not a MAdd/MSub triad. How could I do this by defining such a sequence or the pattern in the .def file itself for the ISD::MUL? Thanks. Girish. >________________________________ > From: Jim Grosbach <grosbach at apple.com> >To: girish gulawani <girishvg at yahoo.com> >Cc: Johannes Birgmeier <e0902998 at student.tuwien.ac.at>; LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >Sent: Wednesday, 21 December 2011 12:41 AM >Subject: Re: [LLVMdev] Stop MachineCSE on certain instructions > >Hi Girish, > >Sorry,...

Hello All. On a particular target the back-end generates an instruction like: beqz      r2, "$BB0_-1"   Is it a back-end specific issue? Could someone please help me figure out how this gets resolved? What confuses me is, all other branches are correctly labelled and resolved!  Thanks. Girish. -------------- next part -------------- An HTML attachment was scrubbed... URL:

May be you have branched to a BB which has been deleted. On 24 January 2012 20:16, girish gulawani <girishvg at yahoo.com> wrote: > > Hello All. > On a particular target the back-end generates an instruction like: > beqz r2, "$BB0_-1" > > Is it a back-end specific issue? Could someone please help me figure out > how this gets resolved? What confuses me is, all other...

...AG thinks its a CSE case. Please note this is not a MAdd/MSub triad. > > How could I do this by defining such a sequence or the pattern in the .def file itself for the ISD::MUL? > Thanks. > Girish. > > From: Jim Grosbach <grosbach at apple.com> > To: girish gulawani <girishvg at yahoo.com> > Cc: Johannes Birgmeier <e0902998 at student.tuwien.ac.at>; LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> > Sent: Wednesday, 21 December 2011 12:41 AM > Subject: Re: [LLVMdev] Stop MachineCSE on certain instructions > > Hi Girish, > > S...

Hi, I am not able to find the documentation on SPEDI. Or the source code for the project. Thanks and Regards, Tarun. On Mon, Jan 9, 2012 at 3:24 PM, girish gulawani <girishvg at yahoo.com> wrote: > > > Hello Tarun. > You mean SPEDI? > http://llvm.org/ProjectsWithLLVM/2003-Fall-CS497YYZ-SPEDI.pdf > > Regards, > Girish. > > *From:* tarun agrawal <tarun at cse.iitb.ac.in> > *To:* llvmdev <llvmdev at cs.uiuc.edu> > *Sent...

...ere I do BuildMI (newOpcode) and followed by br2uncond->eraseFromParent(). This results in br1cond loosing it's label/offset. How could I resolve this? Best regards, Girish. May be you have branched to a BB which has been deleted. > > >On 24 January 2012 20:16, girish gulawani <girishvg at yahoo.com> wrote: > > >> >>Hello All. >>On a particular target the back-end generates an instruction like: >>beqz      r2, "$BB0_-1" >> >>  >>Is it a back-end specific issue? Could someone please help me figure out how this gets resolv...

Hi Girish, Sorry, but I'm afraid I don't understand your question. Can you elaborate a bit? -Jim On Dec 19, 2011, at 9:12 PM, girish gulawani wrote: > > Hello Jim. > Just out of curiosity, won't such mechanism work via the patterns from instructions defs? > > Thanks. > Girish. > > From: Jim Grosbach <grosbach at apple.com> > To: Johannes

Hello Jim. Just out of curiosity, won't such mechanism work via the patterns from instructions defs? Thanks. Girish. >________________________________ > From: Jim Grosbach <grosbach at apple.com> >To: Johannes Birgmeier <e0902998 at student.tuwien.ac.at> >Cc: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >Sent: Monday, 19 December 2011 10:33 PM

Hello All. This is purely from a particular VLIW target back-end perspective. There it is possible to schedule an MI on to one of multiple execution pipes. This leads to a different instruction encoding per the pipe it is bound to, and need to percolate this information down. Would it be advisable to extend and use the "MachineInstr.Flags" field for this purpose? Right now this flag

Hello Chris. Can you please provide the URL where the slides are uploaded? Thanks. Girish. >________________________________ > From: Chris Lattner <clattner at apple.com> >To: Joe Abbey <jabbey at arxan.com> >Cc: "llvmdev at cs.uiuc.edu List" <llvmdev at cs.uiuc.edu> >Sent: Thursday, 5 January 2012 6:27 AM >Subject: Re: [LLVMdev] LLVM Dev Meeting

Hello Anton. Thanks for the comment. > Precisely this is the situation! There're two consecutive branches (br1cond >> and br2uncond). Inside of AnalyzeBranch, there's an opcode swap of br2uncond >> (ex. j_foward to j_backward). There I do BuildMI (newOpcode) and followed by >> br2uncond->eraseFromParent(). This results in br1cond loosing it's >>

Hi Evan. The hasSideEffects method I believe operates only on Inline Assembly (IA) blocks. What if such a sequence is not part of IA? Thanks. Girish. If an instruction is marked as side-effect free then it's a candidate for CSE. Try marking the instruction with hasSideEffects. > >Evan > >On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote: > >> Hello, >>