search for: gich_lrs

Displaying 8 results from an estimated 8 matches for "gich_lrs".

Did you mean: gich_lr
2012 Feb 15
7
[PATCH v3] arm: support fewer LR registers than virtual irqs
If the vgic needs to inject a virtual irq into the guest, but no free LR registers are available, add the irq to a list and return. Whenever an LR register becomes available we add the queued irq to it and remove it from the list. We use the gic lock to protect the list and the bitmask. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> --- xen/arch/arm/gic.c |
2013 Feb 18
2
[PATCH v2 2/4] xen/arm: do not use is_running to decide whether we can write directly to the LR registers
During context switch is_running is set for the next vcpu before the gic state is actually saved. This leads to possible nasty races when interrupts need to be injected after is_running is set to the next vcpu but before the currently running gic state has been saved from the previous vcpu. Use current instead of is_running to check which one is the currently running vcpu: set_current is called
2013 Feb 15
1
[PATCH 3/4] xen/arm: dump gic debug info from arch_dump_domain_info
.../gic.c index 88f2d3a..9db1f57 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -677,6 +677,33 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r } } +void gic_dump_info(struct vcpu *v) +{ + int i; + struct pending_irq *p; + + printk("GICH_LRs (vcpu %d) mask=%llx\n", v->vcpu_id, v->arch.lr_mask); + if ( v == gic_running ) + { + for ( i = 0; i < nr_lrs; i++ ) + printk(" HW_LR[%d]=%x\n", i, GICH[GICH_LR + i]); + } else { + for ( i = 0; i < nr_lrs; i++ ) + printk(&quo...
2013 May 06
2
[PATCH v2] xen/gic: EOI irqs on the right pcpu
We need to write the irq number to GICC_DIR on the physical cpu that previously received the interrupt, but currently we are doing it on the pcpu that received the maintenance interrupt. As a consequence if a vcpu is migrated to a different pcpu, the irq is going to be EOI''ed on the wrong pcpu. This covers the case where dom0 vcpu0 is running on pcpu1 for example (you can test this
2013 May 07
1
[PATCH v3] xen/gic: EOI irqs on the right pcpu
We need to write the irq number to GICC_DIR on the physical cpu that previously received the interrupt, but currently we are doing it on the pcpu that received the maintenance interrupt. As a consequence if a vcpu is migrated to a different pcpu, the irq is going to be EOI''ed on the wrong pcpu. This covers the case where dom0 vcpu0 is running on pcpu1 for example (you can test this
2013 Jun 26
24
Re: [XenARM] XEN tools for ARM with Virtualization Extensions
(moving to xen-devel, xen-arm is for the older PV ARM port) On Tue, 2013-06-25 at 23:59 +0000, Eric Trudeau wrote: > Hi, I am trying to build the XEN tools for our port of XEN to our > Cortex A15-based platform. > > I am using the repo at git://xenbits.xenproject.org/xen.git to > cross-compile the tools into our rootfs. Which branch/changeset are you using? I've heard that
2012 Jan 09
39
[PATCH v4 00/25] xen: ARMv7 with virtualization extensions
Hello everyone, this is the fourth version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See
2011 Dec 06
57
[PATCH RFC 00/25] xen: ARMv7 with virtualization extensions
Hello everyone, this is the very first version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See