Displaying 3 results from an estimated 3 matches for "gic_lr".
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gich_lr
2013 Oct 08
3
Re: [PATCH v4 1/9] xen/arm: Implement hvm save and restore
...>arch.gic_apr;
>> +
>> + /* Save list registers and masks */
>> + /* (it is not necessary to save/restore them, but LR state can have
>> + * influence on downtime after Live Migration (to be tested)
>> + */
>> + memcpy(ctxt.gic_lr, v->arch.gic_lr, sizeof(ctxt.gic_lr));
>> + ctxt.lr_mask = v->arch.lr_mask;
>> + ctxt.event_mask = v->arch.event_mask;
>> +
>> + /* Save PPI states (per-CPU) */
>> + /* It is necessary if SMP enabled */
>> + vgic_irq_ra...
2013 Feb 18
2
[PATCH v2 2/4] xen/arm: do not use is_running to decide whether we can write directly to the LR registers
...*/
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index ac1f939..2d0b052 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -65,11 +65,9 @@ void gic_save_state(struct vcpu *v)
{
int i;
- spin_lock_irq(&gic.lock);
for ( i=0; i<nr_lrs; i++)
v->arch.gic_lr[i] = GICH[GICH_LR + i];
v->arch.lr_mask = this_cpu(lr_mask);
- spin_unlock_irq(&gic.lock);
/* Disable until next VCPU scheduled */
GICH[GICH_HCR] = 0;
isb();
@@ -480,7 +478,7 @@ void gic_set_guest_irq(struct vcpu *v, unsigned int virtual_irq,
spin_lock_irqsave(&...
2013 Feb 15
1
[PATCH 3/4] xen/arm: dump gic debug info from arch_dump_domain_info
..., v->arch.lr_mask);
+ if ( v == gic_running )
+ {
+ for ( i = 0; i < nr_lrs; i++ )
+ printk(" HW_LR[%d]=%x\n", i, GICH[GICH_LR + i]);
+ } else {
+ for ( i = 0; i < nr_lrs; i++ )
+ printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_lr[i]);
+ }
+
+ list_for_each_entry ( p, &v->arch.vgic.inflight_irqs, inflight )
+ {
+ printk("Inflight irq=%d\n", p->irq);
+ }
+
+ list_for_each_entry( p, &v->arch.vgic.lr_pending, lr_queue )
+ {
+ printk("Pending irq=%d\n", p->i...