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So, when the MI scheduler is enabled, will SD scheduling be totally disabled or the SD scheduler will be automatically set to do source scheduling? -Ghassan ________________________________ From: Andrew Trick <atrick at apple.com> To: llvmdev at cs.uiuc.edu Cc: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Sent: Thursday, September 26, 2013 9:24 AM Subject: Re: [LLVMdev] Enabling MI Scheduler on x86 (was Experimental Evaluation of the Schedulers in LLVM 3.3) On Sep 23, 2013, at 11:36 PM, Chandler Carruth <chandlerc at google.com> wrote: > >On Tue, Sep 24, 2013 at...

...omparable size, he may get different execution-time results, but most likely he will get the same spill count results that we got (of course, I mean the relative results). -Ghassan  ________________________________ From: Renato Golin <renato.golin at linaro.org> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: Andrew Trick <atrick at apple.com>; "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> Sent: Thursday, September 19, 2013 8:27 PM Subject: Re: [LLVMdev] Experimental Evaluation of the Schedulers in LLVM 3.3 On 19 September 2013 17:25, Ghassan Shobaki...

...urprising for you? The low impact of the MI scheduler, the relatively good performance of the source scheduler or the relatively poor performance of the ILP scheduler? Thanks -Ghassan  ________________________________ From: Benjamin Kramer <benny.kra at gmail.com> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: Andrew Trick <atrick at apple.com>; "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> Sent: Thursday, September 19, 2013 4:53 PM Subject: Re: [LLVMdev] Experimental Evaluation of the Schedulers in LLVM 3.3 On 17.09.2013, at 20:04, Ghassan Shobaki &lt...

On 26 September 2013 08:30, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > So, when the MI scheduler is enabled, will SD scheduling be totally disabled > or the SD scheduler will be automatically set to do source scheduling? The latter. The SD scheduler is where the DAG is converted into the linear MachineInstr representation. Some kind of...

Thank you for the answers, Jakob! That's really informative for someone who is still new to LLVM like me. Please see my responses below. -Ghassan  ________________________________ From: Jakob Stoklund Olesen <stoklund at 2pi.dk> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> Sent: Tuesday, August 16, 2011 12:52 AM Subject: Re: [LLVMdev] Register Pressure Computation during Pre-Allocation Scheduling On Aug 15, 2011, at 1:27 AM, Ghassan Shobaki wrote: >This information is only...

Hi Renato, Please see my answers below. Thanks -Ghassan ________________________________ From: Renato Golin <renato.golin at linaro.org> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: Andrew Trick <atrick at apple.com>; "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> Sent: Thursday, September 19, 2013 5:30 PM Subject: Re: [LLVMdev] Experimental Evaluation of the Schedulers in LLVM 3.3 On 17 September 2013 19:04, Ghassan Shobaki...

...and experimented with such optimizations in LLVM? Thanks Ghassan Shobaki, PH.D Assistant Professor Department of Computer Science Princess Sumaya University for Technology Amman, Jordan ________________________________ From: Sean Silva <silvas at purdue.edu> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> Sent: Monday, April 15, 2013 5:03 PM Subject: Re: [LLVMdev] Power/Energy Awareness in LLVM See http://llvm.org/bugs/show_bug.cgi?id=6210. -- Sean Silva -------------- next part -------------- An HTML attac...

On 19 September 2013 17:25, Ghassan Shobaki <ghassan_shobaki at yahoo.com>wrote: > Ghassan: You have made me so curious to try other benchmarks in our future > work. Most academic publications on CPU performance though use SPEC. You > can even find some recent publications that are still using SPEC CPU2000! > When I was at AMD in 2009, perfor...

...the latter case, we are willing to test the trunk. Thanks Ghassan Shobaki Assistant Professor Department of Computer Science Princess Sumaya University for Technology Amman, Jordan ________________________________ From: Andrew Trick <atrick at apple.com> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> Sent: Monday, July 1, 2013 8:10 PM Subject: Re: MI Scheduler vs SD Scheduler? Sent from my iPhone On Jun 28, 2013, at 2:38 PM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: Hi, > > &...

On 17 September 2013 19:04, Ghassan Shobaki <ghassan_shobaki at yahoo.com>wrote: > We have done some experimental evaluation of the different schedulers in > LLVM 3.3 (source, BURR, ILP, fast, MI). The evaluation was done on x86-64 > using SPEC CPU2006. We have measured both the amount of spill code as well > as the execution time as detailed...

On 17.09.2013, at 20:04, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Hi Andy, > > We have done some experimental evaluation of the different schedulers in LLVM 3.3 (source, BURR, ILP, fast, MI). The evaluation was done on x86-64 using SPEC CPU2006. We have measured both the amount of spill code as well as the execution time as de...

Hi Andy, We have done some experimental evaluation of the different schedulers in LLVM 3.3 (source, BURR, ILP, fast, MI). The evaluation was done on x86-64 using SPEC CPU2006. We have measured both the amount of spill code as well as the execution time as detailed below. Here are our main findings: 1. The SD schedulers significantly impact the spill counts and the execution times for many

Sent from my iPhone On Jun 28, 2013, at 2:38 PM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Hi, > > We are currently in the process of upgrading from LLVM 2.9 to LLVM 3.3. We are working on instruction scheduling (mainly for register pressure reduction). I have been following the llvmdev mailing list and have learned that a machine instruction (MI) sch...

Hi Andy, Please see my in-line answers below. Regards -Ghassan ________________________________ From: Andrew Trick <atrick at apple.com> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> Sent: Friday, September 23, 2011 8:02 PM Subject: Re: [LLVMdev] Pre-Allocation Schedulers in LLVM On Sep 23, 2011, at 6:16 AM, Ghassan Shobaki wrote: Hi Andrew, > > >What we have is not a patch to a...

...iler. Any truth to this? Can anyone who is interested in performance on x86-64 try rerunning his/her tests using the -m32 mode to see if that gives any speedup? Many thanks! -Ghassan ________________________________ From: Gordon Keiser <gkeiser at arxan.com> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com>; "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> Sent: Monday, January 16, 2012 2:34 AM Subject: RE: [LLVMdev] -march and -mtune options on x86 Which options are you seeing that cause the largest difference, and on which targets?   As Chandler mentioned there...

On Jul 2, 2013, at 2:35 PM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Thank you for the answers! We are currently trying to test the MI scheduler. We are using LLVM 3.3 with Dragon Egg 3.3 on an x86-64 machine. So far, we have run one SPEC CPU2006 test with the MI scheduler enabled using the option -fplugin-arg-dragonegg-llvm-option='...

Hi, We are currently in the process of upgrading from LLVM 2.9 to LLVM 3.3. We are working on instruction scheduling (mainly for register pressure reduction). I have been following the llvmdev mailing list and have learned that a machine instruction (MI) scheduler has been implemented to replace (or work with?) the selection DAG (SD) scheduler. However, I could not find any document that

On Mon, Jan 16, 2012 at 12:29 AM, Ghassan Shobaki <ghassan_shobaki at yahoo.com > wrote: > Let me describe more precisely what I am doing and why the results I got > may help improve LLVM's performance on modern x86-64 processors regardless > of the front end (GCC, Clang or DragonEgg). > > I am running ALL my tests on an Intel Xeon E5540 pro...

On Sep 17, 2013, at 11:04 AM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > 1. The SD schedulers significantly impact the spill counts and the execution times for many benchmarks, but the machine instruction (MI) scheduler in 3.3 has very limited impact on both spill counts and execution times. Is this because most of you work on MI did not ma...

I have been doing some benchmarking on x86 using llvm 2.9 with the llvm-gcc 4.2 front end. I noticed that the -march and -mtune options make a significant positive difference in x86-32 mode but hardly make any difference in x86-64 mode. The small difference that I am measuring when the target is x86-64 could easily be random variation, while for the x86-32 target I am measuring a huge difference