search for: getvr

AddRegisterOperand calls getVR and yes, I think an IMPLICIT_DEF is being generated. On Tue, Aug 25, 2015 at 2:40 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 11:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > I have not tried 3.5, it's a significant amount of wo...

...Colombet <qcolombet at apple.com> wrote: > Oh, could you paste the MIs you get right after ISel (the whole def use > chain of the interesting vregs)? > > Q. > > On Aug 25, 2015, at 12:00 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > AddRegisterOperand calls getVR and yes, I think an IMPLICIT_DEF is being > generated. > > On Tue, Aug 25, 2015 at 2:40 PM, Quentin Colombet <qcolombet at apple.com> > wrote: > >> >> On Aug 25, 2015, at 11:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: >> >> I have not tried 3...

Sorry, still not enough information. I am guessing it's asserting in getVR() called from EmitNode()? The node is CopyToReg and it's trying to find the virtual register of operand 2? From the schedule, I don't see the definition of the operand. Can you do DAG.viewGraph()? That should gives us a better idea. Evan On Oct 16, 2007, at 9:06 PM, Scott Michel wrot...

I have not tried 3.5, it's a significant amount of work to port from one version to the next though, I did not personally do the 3.4 to 3.6 porting. I agree though, it was very strange that it suddenly just changed behavior. It looks like to me that InstrEmitter.cpp:getVR is the one assigning the virtual register no? Though this code in CreateVirtualRegisters: const TargetRegisterClass *RC = TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); That returns GPRBaseRegs for RC, but it then decides to constrain it based on type: if (i < NumR...

Evan: What you requested was in the debug output (sans offending Node), but here it is, outside of the attachment. The offending node is highlighted: SU(0): 0xa908760: ch = EntryToken SU(1): 0xa907600: i32,ch,flag = CopyFromReg 0xa9095d0, 0xa9070e0, 0xa9095d0:1 0xa906e30: ch,flag = CopyToReg 0xa908760, 0xa9070e0, 0xa9071f0 <<--<<--<<--<<--<< Node

...0015671d80: ch = CopyToReg 0x100156463c8, 0x10015677c70, 0x100156749c0 [ORD=49] [ID=1] SU(0): 0x100156762d0: ch = TokenFactor 0x10015678c80, 0x10015679180, 0x10015671d80 [ORD=50] [ID=0] which then asserts: llvm-trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:292: unsigned int llvm::InstrEmitter::getVR(llvm::SDValue, llvm::DenseMap<llvm::SDValue, unsigned int, llvm::DenseMapInfo<llvm::SDValue> >&): Assertion `I != VRBaseMap.end() && "Node emitted out of order - late"' failed. What's gone wrong here? Is the order in the SU wrong, or should the scheduler i...

Hi Ryan, > On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Quentin, > > I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls: > > const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType()); > VReg = MRI->createVirtualRegister(RC); > > My question is why is it using the SimpleValueType to define the register class instead of the actual regis...

...t10: i16,ch,i16 = merge_values t9, t9:2, t9:1 t8: ch = RET Register:i16 %R25R24, t7, t7:1 As you can see, even though the edges are correct, t7 should be after t10. This trips up LLVM further downstream: lib/CodeGen/SelectionDAG/InstrEmitter.cpp:303: unsigned int llvm::InstrEmitter::getVR(llvm::SDValue, llvm::DenseMap<llvm::SDValue, unsigned int>&): Assertion `I != VRBaseMap.end() && "Node emitted out of order - late"' failed. Any idea what might be causing this? Where does the order of nodes come from anyway? Thanks, Gergo

...gt;> //Op.dump(); >> assert(Op.getValueType() != MVT::Other && >> Op.getValueType() != MVT::Glue && >> "Chain and glue operands should occur at end of operand list!"); >> // Get/emit the operand. >> unsigned VReg = getVR(Op, VRBaseMap); >> assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); >> const MCInstrDesc &MCID = MIB->getDesc(); >> bool isOptDef = IIOpNum < MCID.getNumOperands() && >> MCID.OpInfo[IIOpNum].isOptionalDef();...

...t;>>> >>>>> Hi Ryan, >>>>> >>>>> On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: >>>>> >>>>> Quentin, >>>>> >>>>> I apologize for the spamming here but in getVR (where VReg is >>>>> assigned an RC), it calls: >>>>> >>>>> const TargetRegisterClass *RC = >>>>> TLI->getRegClassFor(Op.getSimpleValueType()); >>>>> VReg = MRI->createVirtualRegister(RC); >>>>> >>...

...e.com> >>> wrote: >>> >>>> Hi Ryan, >>>> >>>> On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: >>>> >>>> Quentin, >>>> >>>> I apologize for the spamming here but in getVR (where VReg is assigned >>>> an RC), it calls: >>>> >>>> const TargetRegisterClass *RC = >>>> TLI->getRegClassFor(Op.getSimpleValueType()); >>>> VReg = MRI->createVirtualRegister(RC); >>>> >>>> My question is...

...lt; "Op = "; > //Op.dump(); > assert(Op.getValueType() != MVT::Other && > Op.getValueType() != MVT::Glue && > "Chain and glue operands should occur at end of operand list!"); > // Get/emit the operand. > unsigned VReg = getVR(Op, VRBaseMap); > assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); > const MCInstrDesc &MCID = MIB->getDesc(); > bool isOptDef = IIOpNum < MCID.getNumOperands() && > MCID.OpInfo[IIOpNum].isOptionalDef(); > // If the...

> On Aug 24, 2015, at 1:30 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > I'm trying to do something like this: > > // Dst = NewVReg's reg class > // *II = MCInstrDesc > // IIOpNum = II Operand Num > > if (TRI->getCommonSubClass(DstRC, TRI->getRegClass(II->OpInfo[IIOpNum].RegClass)) == DstRC) > MRI->setRegClass(VReg, DstRC); >