search for: gettarget

was "nv50/ir: PostRaConstantFolding improvements" before. nothing really changed from the last version, just minor things. Karol Herbst (5): nv50/ir: restructure and rename postraconstantfolding pass nv50/ir: implement mad post ra folding for nvc0+ gk110/ir: add LIMM form of mad gm107/ir: add LIMM form of mad nv50/ir: also do PostRaLoadPropagation for FMA

...b8 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp @@ -1144,7 +1144,9 @@ GCRA::RIG_Node::addRegPreference(RIG_Node *node) GCRA::GCRA(Function *fn, SpillCodeInserter& spill) : func(fn), regs(fn->getProgram()->getTarget()), - spill(spill) + spill(spill), + nodeCount(0), + nodes(NULL) { prog = func->getProgram(); -- 2.15.1

...unsigned src, unsigned dst ) { MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst); const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo(); reg_info->copyRegToReg(mbb, iter, dst, src, rc); } But the getRegClass method seems to expect a virtual register. Could someone fix this code for me? I could not find an example in the source of LLVM. Thank you very much, Fernando

...rivers/nouveau/codegen/nv50_ir_ra.cpp index 9d70ec3c9c..e4f38c8e46 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp @@ -1146,6 +1146,9 @@ GCRA::GCRA(Function *fn, SpillCodeInserter& spill) : regs(fn->getProgram()->getTarget()), spill(spill) { + nodeCount = 0; + nodes = NULL; + prog = func->getProgram(); // initialize relative degrees array - i takes away from j -- 2.14.0

...ng_nvc0.cpp @@ -666,8 +666,9 @@ NVC0LoweringPass::handleTEX(TexInstruction *i) const int dim = i->tex.target.getDim() + i->tex.target.isCube(); const int arg = i->tex.target.getArgCount(); const int lyr = arg - (i->tex.target.isMS() ? 2 : 1); + const int chipset = prog->getTarget()->getChipset(); - if (prog->getTarget()->getChipset() >= NVISA_GK104_CHIPSET) { + if (chipset >= NVISA_GK104_CHIPSET) { if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) { WARN("indirect TEX not implemented\n"); } @@ -697,7...

...I see code in the PEI (replaceFrameIndices) that is supposed to track the SP/FP adjustment: ---------------------------------------- void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn, int &SPAdj) { const TargetMachine &TM = Fn.getTarget(); assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!"); const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); const TargetFrameLowering *TFI = TM.getFrameLowering()...

...X86::DL, X86::SIL, X86::DIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL }; GR8Class::iterator GR8Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); if (Subtarget.is64Bit()) return X86_GR8_AO_64; else return begin(); } GR8Class::iterator GR8Class::allocation_order_end(const MachineFunction &MF) const { const Tar...

...can add your pass to the end of X86PassConfig::addPreEmitPass() and it will currently be the last thing to run before the asm printer, but I don’t know if thats a guarantee or not. In theory anyone could add something after the call to preEmitPass and before this code FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer); PM.add(Printer); but if they do you can shout loudly :) Thanks, Pete > > -Andy > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.ui...

...================= > --- lib/CodeGen/LLVMTargetMachine.cpp (revision 44794) > +++ lib/CodeGen/LLVMTargetMachine.cpp (working copy) > @@ -158,7 +158,8 @@ > PM.add(createLowerGCPass()); > > // FIXME: Implement the invoke/unwind instructions! > - PM.add(createLowerInvokePass(getTargetLowering())); > + if (!ExceptionHandling) > + PM.add(createLowerInvokePass(getTargetLowering())); Is this right? > > // Make sure that no unreachable blocks are instruction selected. > PM.add(createUnreachableBlockEliminationPass()); > Index: lib/CodeGen/ELFWriter.cpp &...

Hi everyone, Here's a patch that enables exception handling when jitting. I've copy/pasted _many_code from lib/Codegen/DwarfWriter.cpp, so we may need to factorize it, but the functionality is there and I'm very happy with it :) lli should now be able to execute the output from llvm-gcc when using exceptions (the UnwindInst instruction is not involved in this patch). Just add the

...5,F6,F7,F8,F9,F10,F11,F12,F13, V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, LR,CTR, CR0,CR1,CR5,CR6,CR7} GPRClass::iterator GPRClass::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); const PPCSubtarget &Subtarget = TM.getSubtarget<PPCSubtarget>(); if (Subtarget.isMachoABI()){ return Defs_Macho; } else { return Defs_ELF; } } GPRClass::iterator GPRClass::allocation_order_end(const MachineFunction &MF) const {...

...-- lib/CodeGen/LLVMTargetMachine.cpp (revision 44794) >> +++ lib/CodeGen/LLVMTargetMachine.cpp (working copy) >> @@ -158,7 +158,8 @@ >> PM.add(createLowerGCPass()); >> >> // FIXME: Implement the invoke/unwind instructions! >> - PM.add(createLowerInvokePass(getTargetLowering())); >> + if (!ExceptionHandling) >> + PM.add(createLowerInvokePass(getTargetLowering())); >> > > Is this right? > > >From LowerInvoke.cpp: " This transformation is designed for use by code generators which do not yet support stack unwindin...

...v50_ir.cpp @@ -1249,7 +1249,7 @@ nv50_ir_generate_code(struct nv50_ir_prog_info *info) if (ret < 0) goto out; if (prog->dbgFlags & NV50_IR_DEBUG_VERBOSE) - prog->print(); + prog->print(info->omitLineNum); targ->parseDriverInfo(info); prog->getTarget()->runLegalizePass(prog, nv50_ir::CG_STAGE_PRE_SSA); @@ -1257,13 +1257,13 @@ nv50_ir_generate_code(struct nv50_ir_prog_info *info) prog->convertToSSA(); if (prog->dbgFlags & NV50_IR_DEBUG_VERBOSE) - prog->print(); + prog->print(info->omitLineNum); pro...

> On Sun, 2 Jul 2006, Fernando Magno Quintao Pereira wrote: > > > MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); > > const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst); > > const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo(); > > reg_info->copyRegToReg(mbb, iter, dst, src, rc); > > } > > > > But the getRegClass method seems to expect a virtual register. Could > > someone fix this code for me? I could not find an example in the source of > > LLVM. > > Y...

...break; > > + case OP_AND: > + { > + CmpInstruction *cmp = i->getSrc(t)->getInsn()->asCmp(); > + if (!cmp || cmp->op == OP_SLCT) how about if (cmp == NULL || ...) and kill the same condition later? > + return; > + if (!prog->getTarget()->isOpSupported(cmp->op, TYPE_F32)) > + return; > + if (imm0.reg.data.f32 != 1.0) > + return; > + if (cmp == NULL) > + return; > + if (i->getSrc(t)->getInsn()->dType != TYPE_U32) > + return; > + > + i-&gt...

...PEI (replaceFrameIndices) that is supposed to track the SP/FP adjustment: > > ---------------------------------------- > void PEI::replaceFrameIndices(MachineBasicBlock *BB, > MachineFunction &Fn, int &SPAdj) { > const TargetMachine &TM = Fn.getTarget(); > assert(TM.getRegisterInfo() && > "TM::getRegisterInfo() must be implemented!"); > const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); > const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); > const TargetFrameLowering *TFI = TM.get...

...tructions into an Module so a later Pass can work on them. To do so I load a dummy .ll file created from a main stub, create the needed function stubs (ModulePass), insert Blocks and create instructions using BuildMI. I started with branch instructions:     const TargetMachine &TM = MF.getTarget();     const MCInstrInfo *TII = TM.getMCInstrInfo();     DebugLoc DL;     BuildMI(BB, BB.end(), DL, TII->get(ARM::B)).addMBB(trgBlock); these are working fine. When creating an compare instruction like cmp r0, 1 with:      BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8),...

...--- a/lib/CodeGen/StackSegmenter.cpp +++ b/lib/CodeGen/StackSegmenter.cpp @@ -40,7 +40,10 @@ void StackSegmenter::getAnalysisUsage(AnalysisUsage &info) const { } bool StackSegmenter::runOnMachineFunction(MachineFunction &MF) { - return false; + const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering(); + TFI.adjustForSegmentedStacks(MF); + // adjustForSegmentedStacks always changes the MachineFunction + return true; } FunctionPass *llvm::createStackSegmenter() { -- Sanjoy Das http://playingwithpointers.com

...plemented the method ::eliminateFrameIndex() similar to the Sparc and ARM backend. The method looks like this: // frame pointer is in reg of class mytarget::ARegsRegClass unsigned ScratchReg = MF.getRegInfo().createVirtualRegister(&mytarget::ARegsRegClass); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); BuildMI(*MI.getParent(), II, dl, TII.get(mytarget::ADD_AReg), ScratchReg).addReg(FramePtr).addImm(Offset); // Update the original instruction to use the scratch register. MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false); But for the test case int foo(void) { i...

Hi there, I am doing relocation in my backend by calling my function getAddrNonPic: SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG)const{ SValue Hi=getTarget(N,Ty,DAG, MyBackend::Hi16); SValue Lo=getTarget(N,Ty,DAG, MyBackend::Lo16); return DAG.getNode(ISD::ADD, DL, Ty, DAG.getNode(MyBackend::Hi16, DL, Ty, Hi), DAG.getNode(MyBackend::Lo16, DL, Ty, Ho)); } But sometimes a load instruction is lowered into: (r2=lo16(symbol)) lw r1, r2(Hi16(sy...