search for: getoptlevel

Displaying 20 results from an estimated 26 matches for "getoptlevel".

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2017 Jan 06
3
LLVMTargetMachine with optimization level passed from clang.
Here is a problem scenario. I want to enable a backend pass at -O2 or above. if (TM->getOptLevel() >= CodeGenOpt::Default) addPass(&xxxxx); This pass will be run at -O1 too since clang is creating the TargetMachine with CodeGenOpt::Default for -O1. --Sumanth G -----Original Message----- From: mehdi.amini at apple.com [mailto:mehdi.amini at apple.com] Sent: Friday, January 6, 2017...
2017 Jan 06
2
LLVMTargetMachine with optimization level passed from clang.
getOptLevel() gets the level from TargetMachine which is created by the Backendutil in clang with either "Default", "None" or "Aggressive". Threre is no correspondence for "Less". This boils down to , if I pass "-O1", the Target Machine is created with CodeG...
2017 Jan 06
2
LLVMTargetMachine with optimization level passed from clang.
...optimization level passed > from clang. > > > > On Jan 6, 2017, at 10:56 AM, Sumanth Gundapaneni > <sgundapa at codeaurora.org> wrote: > > > > Here is a problem scenario. > > > > I want to enable a backend pass at -O2 or above. > > if (TM->getOptLevel() >= CodeGenOpt::Default) > > addPass(&xxxxx); > > > > This pass will be run at -O1 too since clang is creating the > TargetMachine with CodeGenOpt::Default for -O1. > > Right, you can’t. Can somebody explain why it's not a bug that -O1 and -O2 are identic...
2011 Feb 23
2
[LLVMdev] CodeGenOpt
...al optimization, fp optimization and memory hierarchy optimization. I would like to replace the existing CodeGenOpt::Level enum with a more general CodeGenOpt class that can track different sets of optimization level. Initially it would look something like this: class CodeGenOpt { ... public getOptLevel() ...; getFPLevel() ...; getMemLevel() ...; }; Does this sound reasonable? -Dave
2013 Nov 23
2
[LLVMdev] prevents instruction-scheduler from interfereing instruction pair
...// Expand pseudo instructions before second scheduling pass. addPass(&ExpandPostRAPseudosID); printAndVerify("After ExpandPostRAPseudos"); // Run pre-sched2 passes. if (addPreSched2()) printAndVerify("After PreSched2 passes"); // Second pass scheduler. if (getOptLevel() != CodeGenOpt::None) { addPass(&PostRASchedulerID); printAndVerify("After PostRAScheduler"); } secondly, psuedo instruction is kind of compiler internal representation. I wish our instruction pair can disclose to programmer. intrinsics can do that. thanks, --lx On Fri...
2013 Jan 07
4
[LLVMdev] instruction scheduling issue
...EmitPass. This will add your annotation pass very late, just before the final code is emitted. If you're using the X86 target, then the class and the function is already there: lib/Target/X86/X86TargetMachine.cpp: bool X86PassConfig::addPreEmitPass() { bool ShouldPrint = false; if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) { addPass(createExecutionDependencyFixPass(&X86::VR128RegClass)); ShouldPrint = true; } if (getX86Subtarget().hasAVX() && UseVZeroUpper) { addPass(createX86IssueVZeroUpperPass()); ShouldPrint = true...
2011 Feb 24
0
[LLVMdev] CodeGenOpt
...hierarchy optimization. > > I would like to replace the existing CodeGenOpt::Level enum with a more > general CodeGenOpt class that can track different sets of optimization > level. Initially it would look something like this: > > class CodeGenOpt { > ... > public > getOptLevel() ...; > getFPLevel() ...; > getMemLevel() ...; > }; > > Does this sound reasonable? I don't think that this is the right way to go. Higher level decisions like that should affect your choice of passes to schedule. -Chris
2011 Feb 24
2
[LLVMdev] CodeGenOpt
Chris Lattner <clattner at apple.com> writes: >> class CodeGenOpt { >> ... >> public >> getOptLevel() ...; >> getFPLevel() ...; >> getMemLevel() ...; >> }; >> >> Does this sound reasonable? > > I don't think that this is the right way to go. Higher level > decisions like that should affect your choice of passes to schedule. But there's no way to...
2013 Nov 23
0
[LLVMdev] prevents instruction-scheduler from interfereing instruction pair
...d scheduling pass. > addPass(&ExpandPostRAPseudosID); > printAndVerify("After ExpandPostRAPseudos"); > > // Run pre-sched2 passes. > if (addPreSched2()) > printAndVerify("After PreSched2 passes"); > > // Second pass scheduler. > if (getOptLevel() != CodeGenOpt::None) { > addPass(&PostRASchedulerID); > printAndVerify("After PostRAScheduler"); > } > > > secondly, psuedo instruction is kind of compiler internal representation. I > wish our instruction pair can disclose to programmer. intrinsics ca...
2017 Jan 05
3
LLVMTargetMachine with optimization level passed from clang.
I want the optimization to be turned on at -O1 and above. In my case, it is a target independent back-end pass. (Eg: MachinePipeliner) On 2017-01-04 18:10, Mehdi Amini wrote: >> On Jan 4, 2017, at 4:03 PM, Sumanth Gundapaneni via llvm-dev >> <llvm-dev at lists.llvm.org> wrote: >> >> I see the BackendUtil.cpp of Clang creates the TargetMachine with >> the
2015 Nov 17
2
Confused on how to do a machinefunction pass
...t; 3. This is going to run after postRAscheduler and before code emission so > I changed the x86TrgetMachine.cpp as follow: > void X86PassConfig::addPreEmitPass() { > /////////////add mypass here/////// > addPass(createwawAnalyzer()); > ////////////////////////////////// > if (getOptLevel() != CodeGenOpt::None) > addPass(createExecutionDependencyFixPass(&X86::VR128RegClass)); > > if (UseVZeroUpper) > addPass(createX86IssueVZeroUpperPass()); > > if (getOptLevel() != CodeGenOpt::None) { > addPass(createX86PadShortFunctions()); > addPass(...
2019 Aug 14
3
ORC v2 question
...vm::orc::JITTargetMachineBuilder::detectHost(); > > JTMB->setCodeGenOptLevel(CodeGenOpt::Default); // <-- Explicitly set Codegen opt level > > auto dataLayout = JTMB->getDefaultDataLayoutForTarget(); > > I am not sure what to make of that. What happens if you print TM->getOptLevel() right before running CodeGen? Once your have explicitly set it I would expect them to be the same for ORCv1 and ORCv2. If they're not then it's a plumbing issue. > I explicitly set TM->Options anyway so maybe I don't need this? Regards Dibyendu
2013 Nov 23
1
[LLVMdev] prevents instruction-scheduler from interfereing instruction pair
...xpandPostRAPseudosID); > > printAndVerify("After ExpandPostRAPseudos"); > > > > // Run pre-sched2 passes. > > if (addPreSched2()) > > printAndVerify("After PreSched2 passes"); > > > > // Second pass scheduler. > > if (getOptLevel() != CodeGenOpt::None) { > > addPass(&PostRASchedulerID); > > printAndVerify("After PostRAScheduler"); > > } > > > > > > secondly, psuedo instruction is kind of compiler internal > representation. I > > wish our instruction pair c...
2015 Nov 17
2
Confused on how to do a machinefunction pass
...un after postRAscheduler and before code emission so >> I changed the x86TrgetMachine.cpp as follow: >> void X86PassConfig::addPreEmitPass() { >> /////////////add mypass here/////// >> addPass(createwawAnalyzer()); >> ////////////////////////////////// >> if (getOptLevel() != CodeGenOpt::None) >> addPass(createExecutionDependencyFixPass(&X86::VR128RegClass)); >> >> if (UseVZeroUpper) >> addPass(createX86IssueVZeroUpperPass()); >> >> if (getOptLevel() != CodeGenOpt::None) { >> addPass(createX86PadShortFun...
2015 Nov 04
3
Confused on how to do a machinefunction pass
Thank you so much. That helped alot. Fami On Wed, Nov 4, 2015 at 9:40 AM, John Criswell <jtcriswel at gmail.com> wrote: > On 11/3/15 7:54 PM, fateme Hoseini wrote: > > Dear John, > Thank you so much for your help. I looked at those documents. Could you > kindly answer the following questions: > > Does it mean that I have to make my own backend target in order to write
2019 Aug 13
4
ORC v2 question
Hi Lang, On Tue, 13 Aug 2019 at 22:03, Lang Hames <lhames at gmail.com> wrote: > When you say your code is not getting optimized, do you mean that IR optimizations are not being applied, or that codegen optimizations are not being applied? > > What do you see if you dump the modules before/after running the pass manager on them, like this: > > dbgs() << "Before
2009 Nov 17
0
[LLVMdev] Getting optimization level in getAnalysisUsage()
Hi, Is it possible to access the optimization level in getAnalysisUsage() on a machine function pass? Once the pass is running, it is available through getAnalysis<MachineFunctionAnalysis>().getOptLevel(). That doesn't work during getAnalysisUsage(), though. /jakob
2011 Feb 24
0
[LLVMdev] CodeGenOpt
On Feb 24, 2011, at 8:14 AM, David A. Greene wrote: > Chris Lattner <clattner at apple.com> writes: > >>> class CodeGenOpt { >>> ... >>> public >>> getOptLevel() ...; >>> getFPLevel() ...; >>> getMemLevel() ...; >>> }; >>> >>> Does this sound reasonable? >> >> I don't think that this is the right way to go. Higher level >> decisions like that should affect your choice of passes to sched...
2013 Jan 07
2
[LLVMdev] instruction scheduling issue
On 1/7/2013 1:53 PM, Sergei Larin wrote: > > Also, how much performance are you willing to sacrifice to do what you > do? Maybe turning off scheduling all together is an acceptable solution? Or insert the calls after scheduling. -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
2013 Jan 07
0
[LLVMdev] instruction scheduling issue
Krzysztof, This would be ideal. How can I do the instrumentation pass after the instruction scheduling? Xu Liu Quoting Krzysztof Parzyszek <kparzysz at codeaurora.org>: > On 1/7/2013 1:53 PM, Sergei Larin wrote: >> >> Also, how much performance are you willing to sacrifice to do what you >> do? Maybe turning off scheduling all together is an acceptable solution?