search for: getmachinenod

...alue op0 = Node->getOperand(2); SDValue op1 = Node->getOperand(3); SDValue op2= Node->getOperand(4); SDValue op3 = Node->getOperand(5); SDValue Ops[]= { op0, op1, op2, op3, Zero, ChainIn }; SDNode *Result = CurDAG->getMachineNode(Mips::BWT_DROP_RESULT, SDLoc(Node), ReturnValueVT, Ops); ReplaceUses(Node, Result); return std::make_pair(true, Result); Any clues on how INTRINSIC_W_CHAIN differs from INTRINSIC_VOID? Thanks, Ambuj Agrawal -------------- next p...

Hi, During instruction selection, I have the following code for certain LOAD instructions: const LoadSDNode *LD = cast<LoadSDNode>(N); SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), VT, PtrVT, MVT::Other, LD->getBasePtr(), LD->getChain()); // Honestly, I have no idea what this does, but other memory // accessing instructions have something similar... MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArra...

...gt; LLVM ERROR: Found 1 machine code errors. This comes from the following four statements in PPCDAGToDAGISel::Select; what's wrong here? SDValue Chain = N->getOperand(0); SDValue Target = N->getOperand(1); unsigned Opc = PPC::MTCTR8; unsigned Reg = PPC::BCTR8; Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target, Chain), 0); return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain); Thanks again, Hal > > /jakob > -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory

On 7/29/2017 1:28 AM, Dr. ERDI Gergo via llvm-dev wrote: > Hi, > > During instruction selection, I have the following code for certain > LOAD instructions: > > const LoadSDNode *LD = cast<LoadSDNode>(N); > SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), > VT, PtrVT, MVT::Other, > LD->getBasePtr(), LD->getChain()); > > // Honestly, I have no idea what this does, but other memory > // accessing instructions have something similar... > MachineSDNode::mmo_iterator MemOp = M...

Is there a generic function that gives the machine instructions and their patterns given in the .td files of a backend specification ? or a subset which match a certain opcode ? otherwise how are the machine instructions being accessed/matched for instruction selection ? -Omer -------------- next part -------------- An HTML attachment was scrubbed... URL:

The reason the ones in PPCInstrInfo.td don't have the patterns to match is the reason they are more analogous to your problem. Namely, tblgen does not have a way to produce nodes with more than one result. The load-with-update instructions do exactly that - one of the inputs is also an output, but the other output is independent (and necessarily a separate register). The FMA variants have

...idReg = X86::ECX; resultReg = X86::EAX; } idRegValue = CurDAG->getRegister(idReg, resultType); SmallVector<SDValue, 8> Ops; SDValue setIdNode = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, idRegValue, id, SDValue()); SDValue rdmsrNode = SDValue(CurDAG->getMachineNode(X86::RDMSR, dl, MVT::Other, setIdNode), 0); SDValue resultNode = CurDAG->getCopyFromReg(rdmsrNode, dl, resultReg, resultType); Ops.push_back(resultNode); Ops.push_back(rdmsrNode); Ops.push_back(setIdNode); SDValue ResultValue = CurDAG->getNode(ISD::TokenFactor, dl, resultTyp...

...Should custom lower this. SDValue Chain = N->getOperand(0); SDValue Target = N->getOperand(1); unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8; Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target, Chain), 0); return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain); } Thanks in advance, Hal On Mon, 2011-12-05 at 13:14 -0600, Hal Finkel wrote: > On Mon, 2011-12-05 at 10:12 -0800, Jakob Stoklund Olesen wrote:...

Hi, I'm working on project which involves writing a backend for a hypothetical architecture. I am currently trying to figure out the best way to translate for loops to use a specialized "loop" instruction the architecture supports. The instruction is similar X86's loop instruction, where a register is automatically decremented and the condition is automatically checked to see if

...CT_ELEMENT, dl, MVT::i32, ValueToBeStored, DAG.getConstant(0, MVT::i32)), DAG.getTargetConstant(SP ::sub0, MVT::i32), DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ValueToBeStored, DAG.getConstant(1, MVT::i32)), DAG.getTargetConstant(SP ::sub1, MVT::i32) }; SDValue NewValueToBeStored = DAG.getMachineNode(TargetOpcode::REG_SEQUENCE, dl, MVT::Untyped, SeqOps); return DAG.getStore(…, NewValueToBeStored, …) The legalizer won’t touch Untyped operands, so once you’ve changed the store operand to this, you won’t have the legalize complain later. But this is very target specific and prone to error if y...

Hi Omer, On Feb 24, 2012, at 8:46 AM, محمد ﻋﻤﺮ ﺩﻫﻠﻮﻯ <omerbeg at gmail.com> wrote: > Is there a generic function that gives the machine instructions and their patterns given in the .td files of a backend specification ? > or a subset which match a certain opcode ? I'm not aware of any dump utility functions to display that information concisely. I agree such a thing would be

...struction selection ? > > > > Have a look at the code in SelectionDAGISel. > > > I am looking at the ARM backend. > In specific, the instruction selection. > In Select(N), I only see ad-hoc matches on the basis of the opcode in the provided SDNode of the DAG, and then getMachineNode() is being used to generate the machine instruction. > Am I understanding this correctly ? > That's just the target-specific part. Also look in lib/CodeGen/SelectionDAG. You may find the debug output from the compiler useful. Try running llc with the "-debug-only=isel" c...

Hi, I got that message from a call to InstrEmitter::AddOperand. I am writing a back end for CortexM0 (for self teaching purposes), I am working on LDR with immediate offset instruction. In the ARM backend, if the offset is 0, the following code is executed by the function ARMDAGToDAGISel::SelectThumbAddrModeImm5S Base = N.getOperand(0); OffImm = CurDAG->getTargetConstant(0, MVT::i32);

...to my target: case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: { SDValue Op1 = N->getOperand(0); SDValue Op2 = N->getOperand(1); unsigned LoReg = R0, HiReg = R1; unsigned Opc = MULRdRr; SDValue InFlag = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, Op1, Op2), 0); // Copy th...

On Sep 9, 2010, at 12:59 PM, Borja Ferrer wrote: > Hello, i've noticed a new possible missed optimization while testing more trivial code. > This time it's not a with a xor but with a multiplication instruction and the example is little bit more involved. > > C code: > > typedef short t; > t foo(t a, t b) > { > t a4 = a*b; > return a4; > } >

On Dec 5, 2011, at 12:56 PM, Hal Finkel wrote: > RegScavenger is complaining about use of an undefined register, CTR8, in > the BCTR8 instruction, in the following instance (this is from the PPC > backend): > > BB#38: derived from LLVM BB %for.end50 > Predecessors according to CFG: BB#36 > %X3<def> = LD 0, <fi#27>; mem:LD8[FixedStack27] >

...idReg = X86::ECX; resultReg = MF.addLiveIn(X86::EAX, &X86::GR32RegClass); } idRegValue = CurDAG->getRegister(idReg, resultType); SDValue setIdNode = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, idRegValue, id, SDValue()); SDValue rdmsrNode = SDValue(CurDAG->getMachineNode(X86::RDMSR, dl, MVT::Glue, setIdNode.getValue(1)), 0); SDValue resultNode = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, X86::EAX, MVT::i32, rdmsrNode); return resultNode.getNode(); but I've a couple of problems: getCopyToReg doesn't show on the final assembly __...

...onstant(0, MVT::i32)), >> DAG.getTargetConstant(SP ::sub0, MVT::i32), >> DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ValueToBeStored, DAG.getConstant(1, MVT::i32)), >> DAG.getTargetConstant(SP ::sub1, MVT::i32) >> }; >> >> SDValue NewValueToBeStored = DAG.getMachineNode(TargetOpcode::REG_SEQUENCE, dl, MVT::Untyped, SeqOps); >> >> return DAG.getStore(…, NewValueToBeStored, …) >> >> The legalizer won’t touch Untyped operands, so once you’ve changed the store operand to this, you won’t have the legalize complain later. But this is very tar...

On Wed, Jun 26, 2019 at 12:38 PM Tim Northover <t.p.northover at gmail.com> wrote: > Hi Gleb, > > On Wed, 26 Jun 2019 at 07:28, Gleb Popov <6yearold at gmail.com> wrote: > > def StoreStackF : InstRI<2, (outs), (ins IntRegs:$reg, i32imm:$i), > > "storestackf $reg, [$i]", [(store_stack i32:$reg, > AddrFI:$i)]>; > > >

On Tue, 30 May 2017, Nemanja Ivanovic wrote: > This is typically accomplished with something like PPC's `RegConstraint` and > `NoEncode`. You can see examples of it that are very similar to what you're after in > PPC's load/store with update forms (i.e. load a value and update the base register > with the effective address - these are used for pre-increment loads/stores).