Displaying 5 results from an estimated 5 matches for "getmachinememoperand".
2013 Jan 18
0
[LLVMdev] llvm backend porting question ,
...) const
{
PR_FUNCTION();
DebugLoc DL;
if (MI != MBB.end()) DL = MI->getDebugLoc();
MachineFunction &MF = *MBB.getParent();MF.dump();
MachineFrameInfo &MFI = *MF.getFrameInfo();
unsigned Align = MFI.getObjectAlignment(MVT::i8);
MachineMemOperand *MMO =
MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MVT::i8),
MachineMemOperand::MOStore,
MFI.getObjectSize(MVT::i8),
Align);
BuildMI(MBB, MI, DL, get(Picoblaze::STORETOSTACK ));//.addMemOperand(MMO);
if (RC == &Picoblaze::G...
2018 Apr 17
1
How to create a proper MachineMemOperand?
Thanks for your advice. But I have searched X86 and find no more
information than I have known.
The problem is not to create a MachineMemOperand, but to create a
MachineMemOperand with certain address. This scene does not exist in the
original code.
Since I have to do this in the process of register allocating, inserting IR
instruction seems to be infeasible. I have thought of storing the address
2011 Jan 25
1
[LLVMdev] Trouble with virtual registers
...etRegisterClass *RC,
const llvm::TargetRegisterInfo*)
const {
DebugLoc DL;
if (MI != MBB.end()) DL = MI->getDebugLoc();
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = *MF.getFrameInfo();
MachineMemOperand *MMO =
MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
MachineMemOperand::MOStore, 0,
MFI.getObjectSize(FrameIdx),
MFI.getObjectAlignment(FrameIdx));
unsigned tmpVReg =
MF.getRegInfo().createVirtualRegister(OURTARGET::IntRe...
2012 Mar 30
1
[LLVMdev] load instruction memory operands value null
Hi,
For a custom target, there is a pass to perform memory dependence analysis, where, i need to get memory pointer for "load instruction". I want to check the pointer alias behavior. I am getting this by considering the memoperands for the load instruction.
For "load instruction", Machine Instruction dumps as below:
vr12<def> = LD_Iri %vr2<kill>, 0;
2014 Mar 07
3
[LLVMdev] [RFC] Add second "failure" AtomicOrdering to cmpxchg instruction
...ailureOrdering,
+ SynchronizationScope SynchScope) {
if (Alignment == 0) // Ensure that codegen never sees alignment 0
Alignment = getEVTAlignment(MemVT);
@@ -4278,15 +4290,16 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT,
MF.getMachineMemOperand(PtrInfo, Flags, MemVT.getStoreSize(), Alignment);
return getAtomic(Opcode, dl, MemVT, Chain, Ptr, Cmp, Swp, MMO,
- Ordering, SynchScope);
+ SuccessOrdering, FailureOrdering, SynchScope);
}
SDValue SelectionDAG::getAtomic(unsigned Opcode, SDLoc dl, EVT M...