search for: getframeregist

...design a situation where you just have 16 live variables instead of taking some random function for gcc (you're implicitly depending on how ra is handling this code instead of forcing a situation where any x86-64 codegen would have to spill). The constness change to TargetRegisterInfo::getFrameRegister looks great, please commit it separately. + /// hasLoadFromStackSlot - If the specified machine instruction is a + /// direct load from a stack slot, return true along with the + /// FrameIndex of the loaded stack slot. If not, return false. + /// Unlike isLoadFromStackSlot, this returns...

What's the "right" way to find out which machine register acts as the stack pointer? I'm working on enhancing Fernando's register allocator debugger and would like to add support for stack pointer semantics. TargetRegisterInfo has a getFrameRegister method but that returns (on x86) either ESP/RSP or EBP/RBP depending on whether frame pointer elimination has been done. Would it be ok to add a getStackPointerRegister method to TargetRegisterInfo? -Dave

...the answer the same for the NVPTX backend? Yes (at least, they have a null TargetRegisterAllocator too). > Maybe something like: targetLacksPhysicalRegissters() would be better? > Maybe. We actually do have "physical" registers called SP and FP (returned by TargetRegisterInfo::getFrameRegister() and used by some default ISel lowerings and by FrameIndex elimination) but of course they aren't really physical registers either. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20151210/67a5c678/attac...

Attached is a patch to print asm comments for spill information. We've discussed the mechanisms before but I wanted to run the patch by everyone before I start to commit pieces. -Dave -------------- next part -------------- A non-text attachment was scrubbed... Name: spillcomments.patch Type: text/x-diff Size: 58930 bytes Desc: not available URL:

...>> >> Yes (at least, they have a null TargetRegisterAllocator too). >> >> Maybe something like: targetLacksPhysicalRegissters() would be better? >> >> Maybe. We actually do have "physical" registers called SP and FP (returned by TargetRegisterInfo::getFrameRegister() and used by some default ISel lowerings and by FrameIndex elimination) but of course they aren't really physical registers either. >> >> >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists.llvm.org <mail...

...if (DVInsn->getNumOperands() == 3) { if (DVInsn->getOperand(0).isReg()) { const MachineOperand RegOp = DVInsn->getOperand(0); const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo(); if (DVInsn->getOperand(1).isImm() && TRI->getFrameRegister(*Asm->MF) == RegOp.getReg()) { unsigned FrameReg = 0; const TargetFrameLowering *TFI = Asm->TM.getFrameLowering(); int Offset = TFI->getFrameIndexReference(*Asm->MF, DVInsn->getOperand(1).getImm(...

...avid Greene wrote: > What's the "right" way to find out which machine register acts as the > stack pointer? I'm working on enhancing Fernando's register allocator > debugger and would like to add support for stack pointer semantics. > > TargetRegisterInfo has a getFrameRegister method but that returns > (on x86) either ESP/RSP or EBP/RBP depending on whether frame > pointer elimination has been done. > > Would it be ok to add a getStackPointerRegister method to TargetRegisterInfo? Why do you need to do this in a register allocator? Typically you want to r...

...e random function for gcc (you're > implicitly depending on how ra is handling this code instead of > forcing a situation where any x86-64 codegen would have to spill). I just took some existing spill tests, but you're point is fair. > The constness change to TargetRegisterInfo::getFrameRegister looks > great, please commit it separately. Will do. > + /// hasLoadFromStackSlot - If the specified machine instruction is a > + /// direct load from a stack slot, return true along with the > + /// FrameIndex of the loaded stack slot. If not, return false. > + /// Unlike i...

On Oct 10, 2011, at 10:26 AM, Richard Osborne wrote: > I'm investigating a bug associated with debug information that manifests > itself in the XCore backend (PR11105). I'd like to understand what the > expected behavior of eliminateFrameIndex() is when it is called on a > dbg_value machine instruction. That is up to the target. The TII::emitFrameIndexDebugValue() hook is

I'm investigating a bug associated with debug information that manifests itself in the XCore backend (PR11105). I'd like to understand what the expected behavior of eliminateFrameIndex() is when it is called on a dbg_value machine instruction. Currently the XCore target replaces the frame index with the frame register and sets the next operand to the byte offset from the frame

Hi all, Virtual ISAs such as WebAssembly and NVPTX use infinite virtual register sets instead of traditional phsyical registers. PrologEpilogInserter is run after register allocation and asserts that all virtuals have been allocated but doesn't otherwise depend on this if scavenging is not needed. We'd like to use the target-independent PEI code for WebAssembly, so we're proposing a

...null TargetRegisterAllocator too). >> >> >> Maybe something like: targetLacksPhysicalRegissters() would be >> better? >> >> >> >> Maybe. We actually do have "physical" registers called SP and FP >> (returned by TargetRegisterInfo::getFrameRegister() and used by some >> default ISel lowerings and by FrameIndex elimination) but of course >> they aren't really physical registers either. >> >> >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists....

...fDebug.cpp @@ -319,9 +319,12 @@ DIE &DwarfDebug::updateSubprogramScopeDIE(DwarfCompileUnit &SPCU, attachLowHighPC(SPCU, *SPDie, FunctionBeginSym, FunctionEndSym); - const TargetRegisterInfo *RI = Asm->TM.getSubtargetImpl()->getRegisterInfo(); - MachineLocation Location(RI->getFrameRegister(*Asm->MF)); - SPCU.addAddress(*SPDie, dwarf::DW_AT_frame_base, Location); + if (SPCU.getCUNode().getEmissionKind() != DIBuilder::LineTablesOnly) { + const TargetRegisterInfo *RI = + Asm->TM.getSubtargetImpl()->getRegisterInfo(); + MachineLocation Location(RI->getFrameRe...

Hi, In the runtime system for GHC Haskell, the stack pointer register is not the same as the one defined by the operating system ABI, and it's difficult for GHC to change that. Following the example of CoreCLR in LLVM, it seems one way to remedy this situation is to define a new ABI (i.e., a new llvm::Triple::EnvironmentType ) and modify the code generator as-needed to respect to our ABI,

...t works now! Our debugger server responds "name:J28;generic:fp;bitsize:32;encoding:uint;format:hex;gcc:60;dwarf:60". And I also set other "generic" attributes like sp, pc, ra, arg1~arg8 to related registers. I dig a little and find llvm dwarf generator uses TargetRegisterInfo::getFrameRegister() to obtain frame base, and uses TargetFrameLowering::getFrameIndexReference() to obtain frame base as well as frame offset of a variable. lldb is OK to check value of variable including both formal arguments and locals, although some line numbers are still improper. For example, in the case men...

Thank you, Clayton. This is very helpful. We use the LLDB specific GDB remote extensions, and our debugger server supports "qRegisterInfo" package. "reg 0x3c" is the frame pointer. In the example mentioned above, we have SP = FP - 40 for current call frame. And variable "a" is stored at address (FP + -24) from asm instruction [FP + -24] = R3;; Thus we can conclude

...rInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo(); >> + >> + // Check for lr dependence >> + if (DepReg == QRI->getRARegister()) { >> + return true; >> + } >> + >> + if (QII->isDeallocRet(MI)) { >> + if (DepReg == QRI->getFrameRegister() || >> + DepReg == QRI->getStackRegister()) >> + return true; >> + } >> + >> + // Check if this is a predicate dependence >> + const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg); >> + if (RC == Hexagon::PredRegsRegi...