search for: getcopytoreg

...register copy so I know it's guaranteed to be loading from the correct register class in the end. I tried mocking this up using the following. (Base is what's returned as the Ax in the move expression above when the DAG is constructed due to SelectAddr().) SDOperand chain = CurDAG->getCopyToReg(Base, M68K::A3, Base); Base = CurDAG->getCopyFromReg(chain, M68K::A3, MVT::i32); This actually generates valid, but horrible code: int deref(int *p) { return *p; } gives move.l a0, a3 -- a0 is a live in (first pointer arg) move.l (a3), d0 -- d0 is a live out (first integer return value...

2008/2/15, Andreas Fredriksson <deplinenoise at gmail.com>: > > I tried mocking this up using the following. (Base is what's returned as > the Ax in the move expression above when the DAG is constructed due to > SelectAddr().) > > SDOperand chain = CurDAG->getCopyToReg(Base, M68K::A3, Base); > Base = CurDAG->getCopyFromReg(chain, M68K::A3, MVT::i32); > Replying to myself here. This worked a bit better :) const unsigned addressReg = RegMap->createVirtualRegister(&M68K::AR32RegClass); SDOperand chain = CurDAG->getCopyToReg(Base, ad...

Thanks to your help I've actually made some progress... Especially the SelectionDAGNodes.h was a good hint. But there are still some things that I can't figure out: // 'mov eax, 41' Chain = DAG.getCopyToReg(Chain, DAG.getRegister(X86::EAX, MVT::i32), DAG.getConstant(41, MVT::i32), InFlag); InFlag = Chain.getValue(1); // 'inc eax' SDValue eaxVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32); SDValue inc = DAG.getNode(ISD::ADD, MVT::i32, eaxVal, DAG.getConstant(1, MVT::i32)); InFla...

On Jul 1, 2009, at 2:22 PMPDT, Dan Gohman wrote: >> Ops.push_back(DAG.getConstant(1, MVT::i32)); >> Chain = DAG.getNode(ISD::ADD, DAG.getVTList(MVT::Other, MVT::i32), >> &Ops[0], Ops.size()); >> >> Isn't that the way how it is supposed to work? > > ADD does not use a chain, so there's no chain operand, or > MVT::Other result for it in an ADD

Hi Andrew, Thank you for the suggestion. I've looked at CodeGenPrepare.cpp and MoveExtToFormExtLoad() is never run. I also notice that the ARM target produces the same additional register usage (copy) and zero extending (of the copy). (See the usage of r3 &r5 and also r12 & r4 in attached file arm-strcspn.s, my understanding is that 'ldrb' is zero extending.) Here is a

...eType(0); if(Subtarget->is64Bit()) { idReg = X86::RCX; resultReg = X86::RAX; } else { idReg = X86::ECX; resultReg = X86::EAX; } idRegValue = CurDAG->getRegister(idReg, resultType); SmallVector<SDValue, 8> Ops; SDValue setIdNode = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, idRegValue, id, SDValue()); SDValue rdmsrNode = SDValue(CurDAG->getMachineNode(X86::RDMSR, dl, MVT::Other, setIdNode), 0); SDValue resultNode = CurDAG->getCopyFromReg(rdmsrNode, dl, resultReg, resultType); Ops.push_back(resultNode); Ops.push_back(rd...

Hi Tim, Tim Northover-2 wrote > The code used for DIV is around X86ISelDAGToDAG.cpp:2415, but from a > glance the key points seem to be: > 1. use the second result of getCopyToReg (i.e. SDValue(setIdNode, 1)) > in the RDMSR node. > 2. Give your RDMSR node type MVT::Glue instead of MVT::Other I tried doing what you said, and the DAG looks like how I think it supposed to look like (attached the picture below). if(Subtarget->is64Bit()) { idReg = X86::RCX;...

On Sep 10, 2013, at 8:59 AM, Robert Lytton <robert at xmos.com> wrote: > Hi, > > A bit more information. > I believe my problem lies with the fact that the load is left as 'anyext from i8'. > On the XCore target we know this will become an 8bit zext load - as there is no 8bit sign extended load! > If BB#1 were to force the load to a "zext from i8" would

...lectionDAGISel class. For efficiency, in order to generate fewer instructions, I would like to assign twice to the same physical register - but since I don't want to "mess" with the register allocator, I am using only virtual registers. However, if I write in my C++ code 2 getCopyToReg() calls to the same virtual register - this gives me the following error: "getVRegDef assumes a single definition or no definition" later, after instruction selection. Therefore, I try to use 2 virtual registers for the same physical register. I know in TablGen instruction specs w...

...e: C source code is: if(...) { a = 1; } else { a = 0; } c = a; It's IR from the front-end is: ... ;<label>:3 store i16 1, i16 *a, align 2 br label %5 ;<label>:4 store i16 0, i16 *a, align 2 br label %5 ;<label>:5 %6 = load i16 *a, align 2 store i16 %6, i16 c I used getCopyToReg in SelectionDAG for store instruction to store value, and getCopyFromReg for load instruction. So, storage values in block '<label>:3' and '<label>:4' are stored in VR0 and VR1 respectively. However, load instruction in block '<label>:5' cannot choose which...

...uction in ISD? I can't find it... Yes. It seems the opcode you want here is ISD::CopyToReg. > 4) Do I get the parameter passing right? Fooling around with other > expressions suggests that I get it wrong. It looks like you have the right idea. For CopyToReg nodes, there's a special getCopyToReg accessor for convenience. > 5) What exactly is the meaning of further result types? If I get the > new > Chain object back, are the other results inside? SDNodes may have multiple results. For example, a LOAD node has two results: the Chain that indicates ordering with respect to other...

Thank you for your help. I think I managed to create the instruction I wanted: // mov eax, 41 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(X86::EAX, MVT::i32), DAG.getConstant(41, MVT::i32), InFlag); InFlag = Chain.getValue(1); I don't understand though what InFlag is for. As I read the code, it even remains uninitialized when first passed to some node creation method. Unfortunately I still don't man...

On 3 December 2012 10:42, Mayur Pandey <mayurthebond at gmail.com> wrote: > So this seems to be the cause of the problem. I guess you're mixing two different problems. First, is the possible lack of conformance with the ABI you state, which I can't comment since I don't know that ABI very well. Second, is the fact that clang is not printing correct debug information (or is

...imately had this before (assuming that RetNode.getOp (1) is not a TargetGlobalAddress or the like) SDOperand OpsTailCall [] = {AdjStackChain, RetNode.getOperand(1), RetNode.getOperand(2)}; RetNode = DCI.DAG.getNode(X86ISD::TAILCALL, TCVTs, OpsTailCall,3); would then be replaced by Chain = DAG.getCopyToReg(AdjStackChain, X86::ECX, RetNode.getOperand (1)); SDOperand OpsTailCall [] = {Chain,DAG.getRegister(X86::ECX, getPointerTy())), RetNode.getOperand(2)}; RetNode = DCI.DAG.getNode(X86ISD::TAILCALL, TCVTs, OpsTailCall, 3); the downside here is that ECX is no longer free for passing function argu...

Greetings, I am rather new to LLVM, so please excuse my limited knowledge about it. Currently I am trying to modify the X86TargetLowering::LowerCALL method by inserting additional instructions before the call. As far as I understand, nodes are created by calling the getNode method on the DAG. If, for example, I insert the following code Ops.push_back(Chain); Chain = DAG.getNode(ISD::TRAP,

Hello, Arnold. > Is there a way to indicate that the register the tail call > instruction uses as destination needs to be valid after the callee > saved registers have been restored? (some X86InstrInfo.td foo magic > maybe ?) It's wrong way to do the things. Because in this case you either violate the ABI for callee, or you're restricted to do tail call lowering only for

...be that somehow the CopyToReg part of the switch statement in ScheduleDAG::EmitNode has a FrameIndex as its second operand. This is especially problematic because the code is either expecting a VirtualRegister or a RegisterSDNode in this location. I've checked all locations where I use the DAG.getCopyToReg function and none of them pass in a frameindex. I explcitily check that I have a register before passing in the value to Register number to CopyToReg, so this leads me to believe that it is being generated somehow by LLVM. In the case I sent earlier in this thread it only occurs when I turn optim...

...de>(AtomicOp.getNode()); SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(AtomicOp), AtomicOp.getValueType(), Node->getChain(), Node->getBasePtr(), Node->getMemoryVT(), Node->getMemOperand()); auto Restore = DAG.getCopyToReg(DAG.getEntryNode(), DL, AVR::SREG, Save); return Load; I can’t figure out how I can glue all these nodes together and return the nonatomic load. How can I do this? Cheers, Dylan ​ -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/piperma...

...terSDNode in this location. I've checked all Unfortunately, I don't think anyone can help you until you can track down what is creating the FrameIndex. Why not set a break point in MachineFrameInfo::CreateFixedObject and CreateStackObject? Evan > > locations where I use the DAG.getCopyToReg function and none of them > pass in a frameindex. I explcitily check that I have a register before > passing in the value to Register number to CopyToReg, so this leads me > to believe that it is being generated somehow by LLVM. > > In the case I sent earlier in this thread it only o...

On Jun 26, 2009, at 4:49 AM, Artjom K. wrote: > > Thank you for your help. > > I think I managed to create the instruction I wanted: > > // mov eax, 41 > Chain = DAG.getCopyToReg(Chain, DAG.getRegister(X86::EAX, MVT::i32), > DAG.getConstant(41, MVT::i32), InFlag); > InFlag = Chain.getValue(1); > > I don't understand though what InFlag is for. As I read the code, it > even > remains uninitialized when first passed to some node creation method. Flag...